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Merge tag 'drm-msm-next-2024-05-07' of https://gitlab.freedesktop.org/drm/msm into drm-next 

Updates for v6.10

Core:
- Switched to generating register header files during build process
  instead of shipping pre-generated headers
- Merged DPU and MDP4 format databases.

DP:
- Stop using compat string to distinguish DP and eDP cases
- Added support for X Elite platform (X1E80100)
- Reworked DP aux/audio support
- Added SM6350 DP to the bindings (no driver changes, using SM8350
  as a fallback compat)

GPU:
- a7xx perfcntr reg fixes
- MAINTAINERS updates
- a750 devcoredump support

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGtpw6dNR9JBikFTQ=TCpt-9FeFW+SGjXWv+Jv3emm0Pbg@mail.gmail.com
This commit is contained in:
Dave Airlie 2024-05-10 10:22:58 +10:00
parent f03eee5fc9 b587f413ca
commit c815e4e79b
138 changed files with 25422 additions and 41424 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
View File

@ -29,6 +29,7 @@ properties:
- qcom,sm8650-dp
- items:
- enum:
- qcom,sm6350-dp
- qcom,sm8150-dp
- qcom,sm8250-dp
- qcom,sm8450-dp

9
Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
View File

@ -53,6 +53,15 @@ patternProperties:
compatible:
const: qcom,sm6350-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,sm6350-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true

20
MAINTAINERS
View File

@ -6816,7 +6816,25 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
F: drivers/gpu/drm/tiny/panel-mipi-dbi.c
DRM DRIVER FOR MSM ADRENO GPU
DRM DRIVER for Qualcomm Adreno GPUs
M: Rob Clark <robdclark@gmail.com>
R: Sean Paul <sean@poorly.run>
R: Konrad Dybcio <konrad.dybcio@linaro.org>
L: linux-arm-msm@vger.kernel.org
L: dri-devel@lists.freedesktop.org
L: freedreno@lists.freedesktop.org
S: Maintained
B: https://gitlab.freedesktop.org/drm/msm/-/issues
T: git https://gitlab.freedesktop.org/drm/msm.git
F: Documentation/devicetree/bindings/display/msm/gpu.yaml
F: drivers/gpu/drm/msm/adreno/
F: drivers/gpu/drm/msm/msm_gpu.*
F: drivers/gpu/drm/msm/msm_gpu_devfreq.*
F: drivers/gpu/drm/msm/msm_ringbuffer.*
F: drivers/gpu/drm/msm/registers/adreno/
F: include/uapi/drm/msm_drm.h
DRM DRIVER for Qualcomm display hardware
M: Rob Clark <robdclark@gmail.com>
M: Abhinav Kumar <quic_abhinavk@quicinc.com>
M: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

1
drivers/gpu/drm/msm/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
generated/

8
drivers/gpu/drm/msm/Kconfig
View File

@ -54,6 +54,14 @@ config DRM_MSM_GPU_SUDO
Only use this if you are a driver developer. This should *not*
be enabled for production kernels. If unsure, say N.
config DRM_MSM_VALIDATE_XML
bool "Validate XML register files against schema"
depends on DRM_MSM && EXPERT
depends on $(success,$(PYTHON3) -c "import lxml")
help
Validate XML files with register definitions against rules-fd schema.
This option is mostly targeting DRM MSM developers. If unsure, say N.
config DRM_MSM_MDSS
bool
depends on DRM_MSM

106
drivers/gpu/drm/msm/Makefile
View File

@ -1,13 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-y := -I $(srctree)/$(src)
ccflags-y += -I $(obj)/generated
ccflags-y += -I $(srctree)/$(src)/disp/dpu1
ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
msm-y := \
adreno-y := \
adreno/adreno_device.o \
adreno/adreno_gpu.o \
adreno/a2xx_gpu.o \
adreno/a2xx_gpummu.o \
adreno/a3xx_gpu.o \
adreno/a4xx_gpu.o \
adreno/a5xx_gpu.o \
@ -17,7 +19,11 @@ msm-y := \
adreno/a6xx_gmu.o \
adreno/a6xx_hfi.o \
msm-$(CONFIG_DRM_MSM_HDMI) += \
adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
adreno-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
msm-display-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi.o \
hdmi/hdmi_audio.o \
hdmi/hdmi_bridge.o \
@ -30,7 +36,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
msm-$(CONFIG_DRM_MSM_MDP4) += \
msm-display-$(CONFIG_DRM_MSM_MDP4) += \
disp/mdp4/mdp4_crtc.o \
disp/mdp4/mdp4_dsi_encoder.o \
disp/mdp4/mdp4_dtv_encoder.o \
@ -41,7 +47,7 @@ msm-$(CONFIG_DRM_MSM_MDP4) += \
disp/mdp4/mdp4_kms.o \
disp/mdp4/mdp4_plane.o \
msm-$(CONFIG_DRM_MSM_MDP5) += \
msm-display-$(CONFIG_DRM_MSM_MDP5) += \
disp/mdp5/mdp5_cfg.o \
disp/mdp5/mdp5_cmd_encoder.o \
disp/mdp5/mdp5_ctl.o \
@ -54,7 +60,7 @@ msm-$(CONFIG_DRM_MSM_MDP5) += \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
msm-$(CONFIG_DRM_MSM_DPU) += \
msm-display-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
disp/dpu1/dpu_encoder.o \
@ -84,14 +90,16 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_writeback.o
msm-$(CONFIG_DRM_MSM_MDSS) += \
msm-display-$(CONFIG_DRM_MSM_MDSS) += \
msm_mdss.o \
msm-y += \
msm-display-y += \
disp/mdp_format.o \
disp/mdp_kms.o \
disp/msm_disp_snapshot.o \
disp/msm_disp_snapshot_util.o \
msm-y += \
msm_atomic.o \
msm_atomic_tracepoints.o \
msm_debugfs.o \
@ -113,14 +121,13 @@ msm-y += \
msm_ringbuffer.o \
msm_submitqueue.o \
msm_gpu_tracepoints.o \
msm_gpummu.o
msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-display-$(CONFIG_DEBUG_FS) += \
dp/dp_debug.o
msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_catalog.o \
dp/dp_ctrl.o \
dp/dp_display.o \
@ -130,21 +137,76 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_audio.o \
dp/dp_utils.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/dsi_cfg.o \
dsi/dsi_host.o \
dsi/dsi_manager.o \
dsi/phy/dsi_phy.o
msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
msm-display-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
msm-display-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
msm-y += $(adreno-y) $(msm-display-y)
obj-$(CONFIG_DRM_MSM) += msm.o
ifeq (y,$(CONFIG_DRM_MSM_VALIDATE_XML))
headergen-opts += --validate
else
headergen-opts += --no-validate
endif
quiet_cmd_headergen = GENHDR $@
cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(srctree)/$(src)/registers/gen_header.py \
$(headergen-opts) --rnn $(srctree)/$(src)/registers --xml $< c-defines > $@
$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
$(src)/registers/adreno/adreno_common.xml \
$(src)/registers/adreno/adreno_pm4.xml \
$(src)/registers/freedreno_copyright.xml \
$(src)/registers/gen_header.py \
$(src)/registers/rules-fd.xsd \
FORCE
$(call if_changed,headergen)
$(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
$(src)/registers/freedreno_copyright.xml \
$(src)/registers/gen_header.py \
$(src)/registers/rules-fd.xsd \
FORCE
$(call if_changed,headergen)
ADRENO_HEADERS = \
generated/a2xx.xml.h \
generated/a3xx.xml.h \
generated/a4xx.xml.h \
generated/a5xx.xml.h \
generated/a6xx.xml.h \
generated/a6xx_gmu.xml.h \
generated/adreno_common.xml.h \
generated/adreno_pm4.xml.h \
DISPLAY_HEADERS = \
generated/dsi_phy_7nm.xml.h \
generated/dsi_phy_10nm.xml.h \
generated/dsi_phy_14nm.xml.h \
generated/dsi_phy_20nm.xml.h \
generated/dsi_phy_28nm_8960.xml.h \
generated/dsi_phy_28nm.xml.h \
generated/dsi.xml.h \
generated/hdmi.xml.h \
generated/mdp4.xml.h \
generated/mdp5.xml.h \
generated/mdp_common.xml.h \
generated/sfpb.xml.h
$(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))
$(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADERS))
targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS)

3251
drivers/gpu/drm/msm/adreno/a2xx.xml.h
View File

File diff suppressed because it is too large Load Diff

4
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
View File

@ -113,7 +113,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
uint32_t *ptr, len;
int i, ret;
msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
a2xx_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
DBG("%s", gpu->name);
@ -469,7 +469,7 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)
static struct msm_gem_address_space *
a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
{
struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);
struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);
struct msm_gem_address_space *aspace;
aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,

4
drivers/gpu/drm/msm/adreno/a2xx_gpu.h
View File

@ -19,4 +19,8 @@ struct a2xx_gpu {
};
#define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base)
struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
dma_addr_t *tran_error);
#endif /* __A2XX_GPU_H__ */

45
drivers/gpu/drm/msm/msm_gpummu.c → drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
View File

@ -5,30 +5,33 @@
#include "msm_drv.h"
#include "msm_mmu.h"
#include "adreno/adreno_gpu.h"
#include "adreno/a2xx.xml.h"
struct msm_gpummu {
#include "adreno_gpu.h"
#include "a2xx_gpu.h"
#include "a2xx.xml.h"
struct a2xx_gpummu {
struct msm_mmu base;
struct msm_gpu *gpu;
dma_addr_t pt_base;
uint32_t *table;
};
#define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base)
#define to_a2xx_gpummu(x) container_of(x, struct a2xx_gpummu, base)
#define GPUMMU_VA_START SZ_16M
#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
#define GPUMMU_PAGE_SIZE SZ_4K
#define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
static void msm_gpummu_detach(struct msm_mmu *mmu)
static void a2xx_gpummu_detach(struct msm_mmu *mmu)
{
}
static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
static int a2xx_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
struct sg_table *sgt, size_t len, int prot)
{
struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
struct sg_dma_page_iter dma_iter;
unsigned prot_bits = 0;
@ -53,9 +56,9 @@ static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
return 0;
}
static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
{
struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
unsigned i;
@ -68,13 +71,13 @@ static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
return 0;
}
static void msm_gpummu_resume_translation(struct msm_mmu *mmu)
static void a2xx_gpummu_resume_translation(struct msm_mmu *mmu)
{
}
static void msm_gpummu_destroy(struct msm_mmu *mmu)
static void a2xx_gpummu_destroy(struct msm_mmu *mmu)
{
struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
DMA_ATTR_FORCE_CONTIGUOUS);
@ -83,16 +86,16 @@ static void msm_gpummu_destroy(struct msm_mmu *mmu)
}
static const struct msm_mmu_funcs funcs = {
.detach = msm_gpummu_detach,
.map = msm_gpummu_map,
.unmap = msm_gpummu_unmap,
.destroy = msm_gpummu_destroy,
.resume_translation = msm_gpummu_resume_translation,
.detach = a2xx_gpummu_detach,
.map = a2xx_gpummu_map,
.unmap = a2xx_gpummu_unmap,
.destroy = a2xx_gpummu_destroy,
.resume_translation = a2xx_gpummu_resume_translation,
};
struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu)
{
struct msm_gpummu *gpummu;
struct a2xx_gpummu *gpummu;
gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
if (!gpummu)
@ -111,10 +114,10 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
return &gpummu->base;
}
void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
dma_addr_t *tran_error)
{
dma_addr_t base = to_msm_gpummu(mmu)->pt_base;
dma_addr_t base = to_a2xx_gpummu(mmu)->pt_base;
*pt_base = base;
*tran_error = base + TABLE_SIZE; /* 32-byte aligned */

3268
drivers/gpu/drm/msm/adreno/a3xx.xml.h
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File diff suppressed because it is too large Load Diff

4379
drivers/gpu/drm/msm/adreno/a4xx.xml.h
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File diff suppressed because it is too large Load Diff

5572
drivers/gpu/drm/msm/adreno/a5xx.xml.h
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File diff suppressed because it is too large Load Diff

11858
drivers/gpu/drm/msm/adreno/a6xx.xml.h
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File diff suppressed because it is too large Load Diff

2
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@ -507,7 +507,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
{
msm_writel(value, ptr + (offset << 2));
writel(value, ptr + (offset << 2));
}
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,

12
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
View File

@ -103,12 +103,12 @@ struct a6xx_gmu {
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
{
return msm_readl(gmu->mmio + (offset << 2));
return readl(gmu->mmio + (offset << 2));
}
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
msm_writel(value, gmu->mmio + (offset << 2));
writel(value, gmu->mmio + (offset << 2));
}
static inline void
@ -131,8 +131,8 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
{
u64 val;
val = (u64) msm_readl(gmu->mmio + (lo << 2));
val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
val = (u64) readl(gmu->mmio + (lo << 2));
val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
return val;
}
@ -143,12 +143,12 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
{
return msm_readl(gmu->rscc + (offset << 2));
return readl(gmu->rscc + (offset << 2));
}
static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
msm_writel(value, gmu->rscc + (offset << 2));
writel(value, gmu->rscc + (offset << 2));
}
#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \

422
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
View File

@ -1,422 +0,0 @@
#ifndef A6XX_GMU_XML
#define A6XX_GMU_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
http://gitlab.freedesktop.org/mesa/mesa/
git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
Copyright (C) 2013-2024 by the following authors:
- Rob Clark <robdclark@gmail.com> Rob Clark
- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef __KERNEL__
#include <linux/bug.h>
#define assert(x) BUG_ON(!(x))
#else
#include <assert.h>
#endif
#ifdef __cplusplus
#define __struct_cast(X)
#else
#define __struct_cast(X) (struct X)
#endif
#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK;
}
#define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000
#define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24
static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
}
#define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
#define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
#define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
#define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00
#define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00
#define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0
#define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8
#define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9
#define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa
#define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc
#define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd
#define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe
#define REG_A6XX_GMU_DCVS_RETURN 0x000023ff
#define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00
#define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01
#define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f
#define REG_A6XX_GMU_CM3_SYSRESET 0x00005000
#define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001
#define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a
#define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c
#define REG_A6XX_GMU_CM3_CFG 0x0000502d
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f
#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10
static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
{
return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK;
}
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14
static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
{
return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK;
}
#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1
#define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2
#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080
#define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4
#define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001
#define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0
#define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4
static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
{
return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK;
}
#define REG_A6XX_GMU_RPMH_CTRL 0x000050e8
#define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001
#define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010
#define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100
#define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200
#define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400
#define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800
#define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000
#define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000
#define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000
#define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000
#define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9
#define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
#define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0
#define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157
#define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158
#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088
#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089
#define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3
#define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180
#define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181
#define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182
#define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183
#define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184
#define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185
#define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186
#define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190
#define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191
#define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192
#define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001
#define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000
#define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193
#define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194
#define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195
#define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
#define REG_A6XX_GMU_GENERAL_0 0x000051c5
#define REG_A6XX_GMU_GENERAL_1 0x000051c6
#define REG_A6XX_GMU_GENERAL_6 0x000051cb
#define REG_A6XX_GMU_GENERAL_7 0x000051cc
#define REG_A7XX_GMU_GENERAL_8 0x000051cd
#define REG_A7XX_GMU_GENERAL_9 0x000051ce
#define REG_A7XX_GMU_GENERAL_10 0x000051cf
#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
#define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558
#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580
#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada
#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957
#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
#define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d
#define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c
#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e
#define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310
#define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314
#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
#define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311
#define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312
#define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a
#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c
#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee
#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496
#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e
#ifdef __cplusplus
#endif
#endif /* A6XX_GMU_XML */

15
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -284,7 +284,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
rbmemptr_stats(ring, index, cpcycles_start));
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
rbmemptr_stats(ring, index, alwayson_start));
@ -330,7 +330,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, 0x00e); /* IB1LIST end */
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
rbmemptr_stats(ring, index, cpcycles_end));
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
rbmemptr_stats(ring, index, alwayson_end));
@ -1255,8 +1255,9 @@ static const u32 a730_protect[] = {
A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
/* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
A6XX_PROTECT_RDONLY(0x008de, 0x0154),
/* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
A6XX_PROTECT_NORDWR(0x008de, 0x0001),
A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
@ -1291,8 +1292,7 @@ static const u32 a730_protect[] = {
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
/* CP_PROTECT_REG[44, 46] are left untouched! */
0,
/* CP_PROTECT_REG[45, 46] are left untouched! */
0,
0,
A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
@ -3062,7 +3062,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
a6xx_llc_slices_destroy(a6xx_gpu);
kfree(a6xx_gpu);
return ERR_PTR(ret);
}

4
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -69,12 +69,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3
static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
{
return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
return readl(a6xx_gpu->llc_mmio + (reg << 2));
}
static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
{
msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
writel(value, a6xx_gpu->llc_mmio + (reg << 2));
}
#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \

83
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
View File

@ -13,15 +13,18 @@
*/
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-variable"
#pragma GCC diagnostic ignored "-Wunused-const-variable"
#include "adreno_gen7_0_0_snapshot.h"
#include "adreno_gen7_2_0_snapshot.h"
#include "adreno_gen7_9_0_snapshot.h"
#pragma GCC diagnostic pop
struct a6xx_gpu_state_obj {
const void *handle;
u32 *data;
u32 count; /* optional, used when count potentially read from hw */
};
struct a6xx_gpu_state {
@ -192,10 +195,10 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
}
#define cxdbg_write(ptr, offset, val) \
msm_writel((val), (ptr) + ((offset) << 2))
writel((val), (ptr) + ((offset) << 2))
#define cxdbg_read(ptr, offset) \
msm_readl((ptr) + ((offset) << 2))
readl((ptr) + ((offset) << 2))
/* read a value from the CX debug bus */
static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
@ -384,21 +387,29 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int debugbus_blocks_count, total_debugbus_blocks;
const u32 *debugbus_blocks;
int debugbus_blocks_count, gbif_debugbus_blocks_count, total_debugbus_blocks;
const u32 *debugbus_blocks, *gbif_debugbus_blocks;
int i;
if (adreno_is_a730(adreno_gpu)) {
debugbus_blocks = gen7_0_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks;
gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
} else if (adreno_is_a740_family(adreno_gpu)) {
debugbus_blocks = gen7_2_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks);
gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks;
gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
} else {
BUG_ON(!adreno_is_a750(adreno_gpu));
debugbus_blocks = gen7_9_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_debugbus_blocks);
gbif_debugbus_blocks = gen7_9_0_gbif_debugbus_blocks;
gbif_debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_gbif_debugbus_blocks);
}
total_debugbus_blocks = debugbus_blocks_count +
ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
total_debugbus_blocks = debugbus_blocks_count + gbif_debugbus_blocks_count;
a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks,
sizeof(*a6xx_state->debugbus));
@ -410,9 +421,9 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
&a6xx_state->debugbus[i]);
}
for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) {
for (i = 0; i < gbif_debugbus_blocks_count; i++) {
a6xx_get_debugbus_block(gpu,
a6xx_state, &a7xx_gbif_debugbus_blocks[i],
a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]],
&a6xx_state->debugbus[i + debugbus_blocks_count]);
}
}
@ -813,10 +824,13 @@ static void a7xx_get_clusters(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
clusters = gen7_0_0_clusters;
clusters_size = ARRAY_SIZE(gen7_0_0_clusters);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
} else if (adreno_is_a740_family(adreno_gpu)) {
clusters = gen7_2_0_clusters;
clusters_size = ARRAY_SIZE(gen7_2_0_clusters);
} else {
BUG_ON(!adreno_is_a750(adreno_gpu));
clusters = gen7_9_0_clusters;
clusters_size = ARRAY_SIZE(gen7_9_0_clusters);
}
a6xx_state->clusters = state_kcalloc(a6xx_state,
@ -948,10 +962,13 @@ static void a7xx_get_shaders(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
shader_blocks = gen7_0_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
} else if (adreno_is_a740_family(adreno_gpu)) {
shader_blocks = gen7_2_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks);
} else {
BUG_ON(!adreno_is_a750(adreno_gpu));
shader_blocks = gen7_9_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_9_0_shader_blocks);
}
a6xx_state->shaders = state_kcalloc(a6xx_state,
@ -1337,10 +1354,13 @@ static void a7xx_get_registers(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
reglist = gen7_0_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
} else if (adreno_is_a740_family(adreno_gpu)) {
reglist = gen7_2_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
} else {
BUG_ON(!adreno_is_a750(adreno_gpu));
reglist = gen7_9_0_reg_list;
pre_crashdumper_regs = gen7_9_0_pre_crashdumper_gpu_registers;
}
count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE;
@ -1388,7 +1408,8 @@ static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu,
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const u32 *regs;
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu) ||
adreno_is_a750(adreno_gpu)));
regs = gen7_0_0_post_crashdumper_registers;
a7xx_get_ahb_gpu_registers(gpu,
@ -1417,16 +1438,18 @@ static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
/* Read a block of data from an indexed register pair */
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_indexed_registers *indexed,
const struct a6xx_indexed_registers *indexed,
struct a6xx_gpu_state_obj *obj)
{
u32 count = indexed->count;
int i;
obj->handle = (const void *) indexed;
if (indexed->count_fn)
indexed->count = indexed->count_fn(gpu);
count = indexed->count_fn(gpu);
obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));
obj->data = state_kcalloc(a6xx_state, count, sizeof(u32));
obj->count = count;
if (!obj->data)
return;
@ -1434,7 +1457,7 @@ static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
gpu_write(gpu, indexed->addr, 0);
/* Read the data - each read increments the internal address by 1 */
for (i = 0; i < indexed->count; i++)
for (i = 0; i < count; i++)
obj->data[i] = gpu_read(gpu, indexed->data);
}
@ -1491,10 +1514,18 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const struct a6xx_indexed_registers *indexed_regs;
int i, indexed_count, mempool_count;
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
if (adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)) {
indexed_regs = a7xx_indexed_reglist;
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
} else {
BUG_ON(!adreno_is_a750(adreno_gpu));
indexed_regs = gen7_9_0_cp_indexed_reg_list;
indexed_count = ARRAY_SIZE(gen7_9_0_cp_indexed_reg_list);
}
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
@ -1507,7 +1538,7 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
/* First read the common regs */
for (i = 0; i < indexed_count; i++)
a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i],
a6xx_get_indexed_regs(gpu, a6xx_state, &indexed_regs[i],
&a6xx_state->indexed_regs[i]);
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
@ -1862,9 +1893,9 @@ static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj,
return;
print_name(p, " - regs-name: ", indexed->name);
drm_printf(p, " dwords: %d\n", indexed->count);
drm_printf(p, " dwords: %d\n", obj->count);
print_ascii85(p, indexed->count << 2, obj->data);
print_ascii85(p, obj->count << 2, obj->data);
}
static void a6xx_show_debugbus_block(const struct a6xx_debugbus_block *block,

14
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
View File

@ -397,7 +397,7 @@ struct a6xx_indexed_registers {
u32 (*count_fn)(struct msm_gpu *gpu);
};
static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@ -408,7 +408,7 @@ static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
};
static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@ -433,12 +433,12 @@ static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
};
static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
};
static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
@ -517,9 +517,9 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
};
static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = {
DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100),
static const u32 a7xx_gbif_debugbus_blocks[] = {
A7XX_DBGBUS_GBIF_CX,
A7XX_DBGBUS_GBIF_GX,
};
static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {

539
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View File

@ -1,539 +0,0 @@
#ifndef ADRENO_COMMON_XML
#define ADRENO_COMMON_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
http://gitlab.freedesktop.org/mesa/mesa/
git clone https://gitlab.freedesktop.org/mesa/mesa.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
*/
#ifdef __KERNEL__
#include <linux/bug.h>
#define assert(x) BUG_ON(!(x))
#else
#include <assert.h>
#endif
#ifdef __cplusplus
#define __struct_cast(X)
#else
#define __struct_cast(X) (struct X)
#endif
enum chip {
A2XX = 2,
A3XX = 3,
A4XX = 4,
A5XX = 5,
A6XX = 6,
A7XX = 7,
};
enum adreno_pa_su_sc_draw {
PC_DRAW_POINTS = 0,
PC_DRAW_LINES = 1,
PC_DRAW_TRIANGLES = 2,
};
enum adreno_compare_func {
FUNC_NEVER = 0,
FUNC_LESS = 1,
FUNC_EQUAL = 2,
FUNC_LEQUAL = 3,
FUNC_GREATER = 4,
FUNC_NOTEQUAL = 5,
FUNC_GEQUAL = 6,
FUNC_ALWAYS = 7,
};
enum adreno_stencil_op {
STENCIL_KEEP = 0,
STENCIL_ZERO = 1,
STENCIL_REPLACE = 2,
STENCIL_INCR_CLAMP = 3,
STENCIL_DECR_CLAMP = 4,
STENCIL_INVERT = 5,
STENCIL_INCR_WRAP = 6,
STENCIL_DECR_WRAP = 7,
};
enum adreno_rb_blend_factor {
FACTOR_ZERO = 0,
FACTOR_ONE = 1,
FACTOR_SRC_COLOR = 4,
FACTOR_ONE_MINUS_SRC_COLOR = 5,
FACTOR_SRC_ALPHA = 6,
FACTOR_ONE_MINUS_SRC_ALPHA = 7,
FACTOR_DST_COLOR = 8,
FACTOR_ONE_MINUS_DST_COLOR = 9,
FACTOR_DST_ALPHA = 10,
FACTOR_ONE_MINUS_DST_ALPHA = 11,
FACTOR_CONSTANT_COLOR = 12,
FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
FACTOR_CONSTANT_ALPHA = 14,
FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
FACTOR_SRC_ALPHA_SATURATE = 16,
FACTOR_SRC1_COLOR = 20,
FACTOR_ONE_MINUS_SRC1_COLOR = 21,
FACTOR_SRC1_ALPHA = 22,
FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
};
enum adreno_rb_surface_endian {
ENDIAN_NONE = 0,
ENDIAN_8IN16 = 1,
ENDIAN_8IN32 = 2,
ENDIAN_16IN32 = 3,
ENDIAN_8IN64 = 4,
ENDIAN_8IN128 = 5,
};
enum adreno_rb_dither_mode {
DITHER_DISABLE = 0,
DITHER_ALWAYS = 1,
DITHER_IF_ALPHA_OFF = 2,
};
enum adreno_rb_depth_format {
DEPTHX_16 = 0,
DEPTHX_24_8 = 1,
DEPTHX_32 = 2,
};
enum adreno_rb_copy_control_mode {
RB_COPY_RESOLVE = 1,
RB_COPY_CLEAR = 2,
RB_COPY_DEPTH_STENCIL = 5,
};
enum a3xx_rop_code {
ROP_CLEAR = 0,
ROP_NOR = 1,
ROP_AND_INVERTED = 2,
ROP_COPY_INVERTED = 3,
ROP_AND_REVERSE = 4,
ROP_INVERT = 5,
ROP_XOR = 6,
ROP_NAND = 7,
ROP_AND = 8,
ROP_EQUIV = 9,
ROP_NOOP = 10,
ROP_OR_INVERTED = 11,
ROP_COPY = 12,
ROP_OR_REVERSE = 13,
ROP_OR = 14,
ROP_SET = 15,
};
enum a3xx_render_mode {
RB_RENDERING_PASS = 0,
RB_TILING_PASS = 1,
RB_RESOLVE_PASS = 2,
RB_COMPUTE_PASS = 3,
};
enum a3xx_msaa_samples {
MSAA_ONE = 0,
MSAA_TWO = 1,
MSAA_FOUR = 2,
MSAA_EIGHT = 3,
};
enum a3xx_threadmode {
MULTI = 0,
SINGLE = 1,
};
enum a3xx_instrbuffermode {
CACHE = 0,
BUFFER = 1,
};
enum a3xx_threadsize {
TWO_QUADS = 0,
FOUR_QUADS = 1,
};
enum a3xx_color_swap {
WZYX = 0,
WXYZ = 1,
ZYXW = 2,
XYZW = 3,
};
enum a3xx_rb_blend_opcode {
BLEND_DST_PLUS_SRC = 0,
BLEND_SRC_MINUS_DST = 1,
BLEND_DST_MINUS_SRC = 2,
BLEND_MIN_DST_SRC = 3,
BLEND_MAX_DST_SRC = 4,
};
enum a4xx_tess_spacing {
EQUAL_SPACING = 0,
ODD_SPACING = 2,
EVEN_SPACING = 3,
};
enum a5xx_address_mode {
ADDR_32B = 0,
ADDR_64B = 1,
};
enum a5xx_line_mode {
BRESENHAM = 0,
RECTANGULAR = 1,
};
enum a6xx_tex_prefetch_cmd {
TEX_PREFETCH_UNK0 = 0,
TEX_PREFETCH_SAM = 1,
TEX_PREFETCH_GATHER4R = 2,
TEX_PREFETCH_GATHER4G = 3,
TEX_PREFETCH_GATHER4B = 4,
TEX_PREFETCH_GATHER4A = 5,
TEX_PREFETCH_UNK6 = 6,
TEX_PREFETCH_UNK7 = 7,
};
#define REG_AXXX_CP_RB_BASE 0x000001c0
#define REG_AXXX_CP_RB_CNTL 0x000001c1
#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
{
return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
}
#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
{
return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
}
#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
{
return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
}
#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
{
return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
}
#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
{
assert(!(val & 0x3));
return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
}
#define REG_AXXX_CP_RB_RPTR 0x000001c4
#define REG_AXXX_CP_RB_WPTR 0x000001c5
#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
{
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
}
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
{
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
}
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
{
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
}
#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
{
return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
}
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
{
return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
}
#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
}
#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
}
#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
}
#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
{
return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
}
#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
{
return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
}
#define REG_AXXX_SCRATCH_UMSK 0x000001dc
#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
{
return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
}
#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
{
return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
}
#define REG_AXXX_SCRATCH_ADDR 0x000001dd
#define REG_AXXX_CP_ME_RDADDR 0x000001ea
#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
#define REG_AXXX_CP_INT_CNTL 0x000001f2
#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000
#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000
#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000
#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000
#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000
#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000
#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000
#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000
#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000
#define REG_AXXX_CP_INT_STATUS 0x000001f3
#define REG_AXXX_CP_INT_ACK 0x000001f4
#define REG_AXXX_CP_ME_CNTL 0x000001f6
#define AXXX_CP_ME_CNTL_BUSY 0x20000000
#define AXXX_CP_ME_CNTL_HALT 0x10000000
#define REG_AXXX_CP_ME_STATUS 0x000001f7
#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
#define REG_AXXX_CP_DEBUG 0x000001fc
#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
}
#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
}
#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
}
#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
}
#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
}
#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
{
return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
}
#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
#define REG_AXXX_CP_ST_BASE 0x0000044d
#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
#define REG_AXXX_CP_MEQ_STAT 0x0000044f
#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
#define REG_AXXX_CP_IB1_BASE 0x00000458
#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
#define REG_AXXX_CP_IB2_BASE 0x0000045a
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
#define REG_AXXX_CP_STAT 0x0000047f
#define AXXX_CP_STAT_CP_BUSY 0x80000000
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
#define AXXX_CP_STAT_ME_BUSY 0x04000000
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
#ifdef __cplusplus
#endif
#endif /* ADRENO_COMMON_XML */

1446
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h Normal file
View File

File diff suppressed because it is too large Load Diff

2803
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View File

File diff suppressed because it is too large Load Diff

12
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View File

@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
&format->base.pixel_format, format->alpha_enable, blend_op);
&format->pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
struct dpu_format *format,
const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
format->base.pixel_format,
format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
struct dpu_format *format;
const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
format = msm_framebuffer_format(pstate->base.fb);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;

24
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
View File

@ -675,7 +675,7 @@ static int dpu_encoder_virt_atomic_check(
if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
fb = conn_state->writeback_job->fb;
if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))
if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
topology.needs_cdm = true;
} else if (disp_info->intf_type == INTF_DP) {
if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
@ -2184,7 +2184,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
}
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
const struct dpu_format *dpu_fmt,
const struct msm_format *dpu_fmt,
u32 output_type)
{
struct dpu_hw_cdm *hw_cdm;
@ -2202,9 +2202,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
if (!hw_cdm)
return;
if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
dpu_fmt->base.pixel_format);
if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
&dpu_fmt->pixel_format);
if (hw_cdm->ops.bind_pingpong_blk)
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
@ -2217,25 +2217,25 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
cdm_cfg->output_fmt = dpu_fmt;
cdm_cfg->output_type = output_type;
cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
/* enable 10 bit logic */
switch (cdm_cfg->output_fmt->chroma_sample) {
case DPU_CHROMA_RGB:
case CHROMA_FULL:
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
case DPU_CHROMA_H2V1:
case CHROMA_H2V1:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
case DPU_CHROMA_420:
case CHROMA_420:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
break;
case DPU_CHROMA_H1V2:
case CHROMA_H1V2:
default:
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
DRMID(phys_enc->parent));
@ -2244,9 +2244,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
break;
}
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
DRMID(phys_enc->parent), cdm_cfg->output_width,
cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);

2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
View File

@ -393,7 +393,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
* @output_type: HDMI/WB
*/
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
const struct dpu_format *dpu_fmt,
const struct msm_format *dpu_fmt,
u32 output_type);
/**

3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
View File

@ -448,9 +448,6 @@ static void dpu_encoder_phys_cmd_enable_helper(
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
return;
ctl = phys_enc->hw_ctl;
ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
}

8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
View File

@ -235,7 +235,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
{
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
const struct dpu_format *fmt = NULL;
const struct msm_format *fmt = NULL;
u32 fmt_fourcc;
unsigned long lock_flags;
struct dpu_hw_intf_cfg intf_cfg = { 0 };
@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
fmt = dpu_get_dpu_format(fmt_fourcc);
fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@ -409,12 +409,12 @@ end:
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_ctl *ctl;
const struct dpu_format *fmt;
const struct msm_format *fmt;
u32 fmt_fourcc;
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
fmt = dpu_get_dpu_format(fmt_fourcc);
fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "\n");

12
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
View File

@ -322,11 +322,11 @@ static void dpu_encoder_phys_wb_setup(
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
struct drm_writeback_job *wb_job;
const struct msm_format *format;
const struct dpu_format *dpu_fmt;
const struct msm_format *dpu_fmt;
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier);
dpu_fmt = mdp_get_format(&phys_enc->dpu_kms->base, format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@ -576,11 +576,11 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
wb_cfg->dest.format = dpu_get_dpu_format_ext(
format->pixel_format, job->fb->modifier);
wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base,
format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
DPU_ERROR("failed to get format %x\n", format->pixel_format);
DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format);
return;
}
@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);

660
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
View File

@ -11,178 +11,11 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
#define DPU_UBWC_META_MACRO_W_H 16
#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
#define DPU_TILE_HEIGHT_DEFAULT 1
#define DPU_TILE_HEIGHT_TILED 4
#define DPU_TILE_HEIGHT_UBWC 4
#define DPU_TILE_HEIGHT_NV12 8
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
/*
* DPU supported format packing, bpp, and other format
* information.
* DPU currently only supports interleaved RGB formats
* UBWC support for a pixel format is indicated by the flag,
* there is additional meta data plane for such formats
*/
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
.chroma_sample = DPU_CHROMA_RGB, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
alpha, bp, flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
.chroma_sample = DPU_CHROMA_RGB, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = th \
}
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
alpha, chroma, count, bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = th \
}
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = th \
}
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_planes = DPU_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
.bits = { g, b, r, a }, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
.flag = {(flg)}, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
/*
* struct dpu_media_color_map - maps drm format to media format
* @format: DRM base pixel format
@ -193,380 +26,11 @@ struct dpu_media_color_map {
uint32_t color;
};
static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB888,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 3, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR888,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 3, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB565,
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR565,
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB1555,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR1555,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA5551,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA5551,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB1555,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR1555,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX5551,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX5551,
COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX4444,
COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA1010102,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, DPU_FORMAT_FLAG_DX,
DPU_FETCH_LINEAR, 1),
PSEUDO_YUV_FMT(NV12,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C1_B_Cb,
DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C1_B_Cb,
DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
PLANAR_YUV_FMT(YUV420,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C1_B_Cb, C0_G_Y,
false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr, C0_G_Y,
false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 3),
};
/*
* UBWC formats table:
* This table holds the UBWC formats supported.
* If a compression ratio needs to be used for this or any other format,
* the data will be passed by user-space.
*/
static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* ARGB8888 and ABGR8888 purposely have the same color
* ordering. The hardware only supports ABGR8888 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
* ordering. The hardware only supports ARGB2101010 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
};
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
static void _dpu_get_v_h_subsample_rate(
enum dpu_chroma_samp_type chroma_sample,
enum mdp_chroma_samp_type chroma_sample,
uint32_t *v_sample,
uint32_t *h_sample)
{
@ -574,15 +38,15 @@ static void _dpu_get_v_h_subsample_rate(
return;
switch (chroma_sample) {
case DPU_CHROMA_H2V1:
case CHROMA_H2V1:
*v_sample = 1;
*h_sample = 2;
break;
case DPU_CHROMA_H1V2:
case CHROMA_H1V2:
*v_sample = 2;
*h_sample = 1;
break;
case DPU_CHROMA_420:
case CHROMA_420:
*v_sample = 2;
*h_sample = 2;
break;
@ -593,7 +57,7 @@ static void _dpu_get_v_h_subsample_rate(
}
}
static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
{
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
@ -609,10 +73,10 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
int color_fmt = -1;
int i;
if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
fmt->base.pixel_format == DRM_FORMAT_P010) {
if (DPU_FORMAT_IS_DX(fmt)) {
if (fmt->unpack_tight)
if (fmt->pixel_format == DRM_FORMAT_NV12 ||
fmt->pixel_format == DRM_FORMAT_P010) {
if (MSM_FORMAT_IS_DX(fmt)) {
if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
color_fmt = COLOR_FMT_P010_UBWC;
@ -622,7 +86,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) {
if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
color_fmt = dpu_media_ubwc_map[i].color;
break;
}
@ -630,14 +94,14 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
static int _dpu_format_get_plane_sizes_ubwc(
const struct dpu_format *fmt,
const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout)
{
int i;
int color;
bool meta = DPU_FORMAT_IS_UBWC(fmt);
bool meta = MSM_FORMAT_IS_UBWC(fmt);
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
layout->format = fmt;
@ -647,12 +111,12 @@ static int _dpu_format_get_plane_sizes_ubwc(
color = _dpu_format_get_media_color_ubwc(fmt);
if (color < 0) {
DRM_ERROR("UBWC format not supported for fmt: %4.4s\n",
(char *)&fmt->base.pixel_format);
DRM_ERROR("UBWC format not supported for fmt: %p4cc\n",
&fmt->pixel_format);
return -EINVAL;
}
if (DPU_FORMAT_IS_YUV(layout->format)) {
if (MSM_FORMAT_IS_YUV(layout->format)) {
uint32_t y_sclines, uv_sclines;
uint32_t y_meta_scanlines = 0;
uint32_t uv_meta_scanlines = 0;
@ -709,7 +173,7 @@ done:
}
static int _dpu_format_get_plane_sizes_linear(
const struct dpu_format *fmt,
const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout,
@ -724,7 +188,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) {
if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@ -742,8 +206,8 @@ static int _dpu_format_get_plane_sizes_linear(
return -EINVAL;
}
if ((fmt->base.pixel_format == DRM_FORMAT_NV12) &&
(DPU_FORMAT_IS_DX(fmt)))
if ((fmt->pixel_format == DRM_FORMAT_NV12) &&
(MSM_FORMAT_IS_DX(fmt)))
bpp = 2;
layout->plane_pitch[0] = width * bpp;
layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample;
@ -751,7 +215,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
@ -781,7 +245,7 @@ static int _dpu_format_get_plane_sizes_linear(
}
static int dpu_format_get_plane_sizes(
const struct dpu_format *fmt,
const struct msm_format *fmt,
const uint32_t w,
const uint32_t h,
struct dpu_hw_fmt_layout *layout,
@ -797,7 +261,7 @@ static int dpu_format_get_plane_sizes(
return -ERANGE;
}
if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt))
if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout);
return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
@ -823,10 +287,10 @@ static int _dpu_format_populate_addrs_ubwc(
return -EFAULT;
}
meta = DPU_FORMAT_IS_UBWC(layout->format);
meta = MSM_FORMAT_IS_UBWC(layout->format);
/* Per-format logic for verifying active planes */
if (DPU_FORMAT_IS_YUV(layout->format)) {
if (MSM_FORMAT_IS_YUV(layout->format)) {
/************************************************/
/* UBWC ** */
/* buffer ** DPU PLANE */
@ -942,7 +406,7 @@ int dpu_format_populate_layout(
return -ERANGE;
}
layout->format = to_dpu_format(msm_framebuffer_format(fb));
layout->format = msm_framebuffer_format(fb);
/* Populate the plane sizes etc via get_format */
ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height,
@ -951,8 +415,8 @@ int dpu_format_populate_layout(
return ret;
/* Populate the addresses given the fb */
if (DPU_FORMAT_IS_UBWC(layout->format) ||
DPU_FORMAT_IS_TILE(layout->format))
if (MSM_FORMAT_IS_UBWC(layout->format) ||
MSM_FORMAT_IS_TILE(layout->format))
ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout);
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
@ -962,23 +426,21 @@ int dpu_format_populate_layout(
int dpu_format_check_modified_format(
const struct msm_kms *kms,
const struct msm_format *msm_fmt,
const struct msm_format *fmt,
const struct drm_mode_fb_cmd2 *cmd,
struct drm_gem_object **bos)
{
const struct drm_format_info *info;
const struct dpu_format *fmt;
struct dpu_hw_fmt_layout layout;
uint32_t bos_total_size = 0;
int ret, i;
if (!msm_fmt || !cmd || !bos) {
if (!fmt || !cmd || !bos) {
DRM_ERROR("invalid arguments\n");
return -EINVAL;
}
fmt = to_dpu_format(msm_fmt);
info = drm_format_info(fmt->base.pixel_format);
info = drm_format_info(fmt->pixel_format);
if (!info)
return -EINVAL;
@ -1004,65 +466,3 @@ int dpu_format_check_modified_format(
return 0;
}
const struct dpu_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier)
{
uint32_t i = 0;
const struct dpu_format *fmt = NULL;
const struct dpu_format *map = NULL;
ssize_t map_size = 0;
/*
* Currently only support exactly zero or one modifier.
* All planes use the same modifier.
*/
DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
switch (modifier) {
case 0:
map = dpu_format_map;
map_size = ARRAY_SIZE(dpu_format_map);
break;
case DRM_FORMAT_MOD_QCOM_COMPRESSED:
map = dpu_format_map_ubwc;
map_size = ARRAY_SIZE(dpu_format_map_ubwc);
DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
(char *)&format);
break;
default:
DPU_ERROR("unsupported format modifier %llX\n", modifier);
return NULL;
}
for (i = 0; i < map_size; i++) {
if (format == map[i].base.pixel_format) {
fmt = &map[i];
break;
}
}
if (fmt == NULL)
DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
(char *)&format, modifier);
else
DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
(char *)&format, modifier,
DPU_FORMAT_IS_UBWC(fmt),
DPU_FORMAT_IS_YUV(fmt));
return fmt;
}
const struct msm_format *dpu_get_msm_format(
struct msm_kms *kms,
const uint32_t format,
const uint64_t modifiers)
{
const struct dpu_format *fmt = dpu_get_dpu_format_ext(format,
modifiers);
if (fmt)
return &fmt->base;
return NULL;
}

25
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
View File

@ -9,17 +9,6 @@
#include "msm_gem.h"
#include "dpu_hw_mdss.h"
/**
* dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
* @format: DRM FourCC Code
* @modifiers: format modifier array from client, one per plane
*/
const struct dpu_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier);
#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0)
/**
* dpu_find_format - validate if the pixel format is supported
* @format: dpu format
@ -42,23 +31,11 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats,
return false;
}
/**
* dpu_get_msm_format - get an dpu_format by its msm_format base
* callback function registers with the msm_kms layer
* @kms: kms driver
* @format: DRM FourCC Code
* @modifiers: data layout modifier
*/
const struct msm_format *dpu_get_msm_format(
struct msm_kms *kms,
const uint32_t format,
const uint64_t modifiers);
/**
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
* @kms: kms driver
* @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format
* @msm_fmt: pointer to the msm_fmt base pointer of an msm_format
* @cmd: fb_cmd2 structure user request
* @bos: gem buffer object list
*

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
View File

@ -170,7 +170,7 @@ static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *
static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
const struct dpu_format *fmt;
const struct msm_format *fmt;
u32 opmode = 0;
u32 csc = 0;
@ -179,14 +179,14 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
fmt = cdm->output_fmt;
if (!DPU_FORMAT_IS_YUV(fmt))
if (!MSM_FORMAT_IS_YUV(fmt))
return -EINVAL;
dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);
dpu_hw_cdm_setup_cdwn(ctx, cdm);
if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
if (fmt->chroma_sample == DPU_CHROMA_H1V2)
if (fmt->chroma_sample == CHROMA_H1V2)
return -EINVAL; /*unsupported format */
opmode = CDM_HDMI_PACK_OP_MODE_EN;
opmode |= (fmt->chroma_sample << 1);

4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
View File

@ -19,7 +19,7 @@ struct dpu_hw_cdm;
* @output_bit_depth: output bit-depth of CDM block
* @h_cdwn_type: downsample type used for horizontal pixels
* @v_cdwn_type: downsample type used for vertical pixels
* @output_fmt: handle to dpu_format of CDM block
* @output_fmt: handle to msm_format of CDM block
* @csc_cfg: handle to CSC matrix programmed for CDM block
* @output_type: interface to which CDM is paired (HDMI/WB)
* @pp_id: ping-pong block to which CDM is bound to
@ -30,7 +30,7 @@ struct dpu_hw_cdm_cfg {
u32 output_bit_depth;
u32 h_cdwn_type;
u32 v_cdwn_type;
const struct dpu_format *output_fmt;
const struct msm_format *output_fmt;
const struct dpu_csc_cfg *csc_cfg;
u32 output_type;
int pp_id;

9
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
View File

@ -545,6 +545,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
u32 intf_active = 0;
u32 dsc_active = 0;
u32 wb_active = 0;
u32 mode_sel = 0;
@ -560,6 +561,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
if (cfg->intf)
intf_active |= BIT(cfg->intf - INTF_0);
@ -567,17 +569,18 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->wb)
wb_active |= BIT(cfg->wb - WB_0);
if (cfg->dsc)
dsc_active |= cfg->dsc;
DPU_REG_WRITE(c, CTL_TOP, mode_sel);
DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
if (cfg->dsc)
DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
if (cfg->cdm)
DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
}

4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
View File

@ -223,9 +223,11 @@ static void dpu_core_irq_callback_handler(struct dpu_kms *dpu_kms, unsigned int
VERB("IRQ=[%d, %d]\n", DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
if (!irq_entry->cb)
if (!irq_entry->cb) {
DRM_ERROR("no registered cb, IRQ=[%d, %d]\n",
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
return;
}
atomic_inc(&irq_entry->count);

30
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View File

@ -96,11 +96,11 @@
#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12)
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
const struct dpu_format *fmt)
const struct msm_format *fmt)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
struct dpu_hw_blk_reg_map *c = &intf->hw;
u32 hsync_period, vsync_period;
u32 display_v_start, display_v_end;
u32 hsync_start_x, hsync_end_x;
@ -118,7 +118,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
/* read interface_cfg */
intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
if (ctx->cap->type == INTF_DP)
if (intf->cap->type == INTF_DP)
dp_intf = true;
hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
@ -194,16 +194,16 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(p->vsync_polarity << 1) | /* VSYNC Polarity */
(p->hsync_polarity << 0); /* HSYNC Polarity */
if (!DPU_FORMAT_IS_YUV(fmt))
panel_format = (fmt->bits[C0_G_Y] |
(fmt->bits[C1_B_Cb] << 2) |
(fmt->bits[C2_R_Cr] << 4) |
if (!MSM_FORMAT_IS_YUV(fmt))
panel_format = (fmt->bpc_g_y |
(fmt->bpc_b_cb << 2) |
(fmt->bpc_r_cr << 4) |
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
panel_format = (COLOR_8BIT |
(COLOR_8BIT << 2) |
(COLOR_8BIT << 4) |
panel_format = (BPC8 |
(BPC8 << 2) |
(BPC8 << 4) |
(0x21 << 8));
DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
@ -223,7 +223,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) {
/*
* DATA_HCTL_EN controls data timing which can be different from
* video timing. It is recommended to enable it for all cases, except
@ -518,10 +518,10 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
}
static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf,
struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg)
{
u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2);
if (cmd_mode_cfg->data_compress)
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
@ -529,7 +529,7 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
if (cmd_mode_cfg->wide_bus_en)
intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2);
}
struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
View File

@ -81,7 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
const struct dpu_format *fmt);
const struct msm_format *fmt);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);

124
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
View File

@ -10,6 +10,8 @@
#include "msm_drv.h"
#include "disp/mdp_format.h"
#define DPU_DBG_NAME "dpu"
#define DPU_NONE 0
@ -35,28 +37,6 @@
#define DPU_MAX_DE_CURVES 3
#endif
enum dpu_format_flags {
DPU_FORMAT_FLAG_YUV_BIT,
DPU_FORMAT_FLAG_DX_BIT,
DPU_FORMAT_FLAG_COMPRESSED_BIT,
DPU_FORMAT_FLAG_BIT_MAX,
};
#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
#define DPU_FORMAT_IS_YUV(X) \
(test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
#define DPU_FORMAT_IS_DX(X) \
(test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
#define DPU_FORMAT_IS_TILE(X) \
(((X)->fetch_mode == DPU_FETCH_UBWC) && \
!test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_FORMAT_IS_UBWC(X) \
(((X)->fetch_mode == DPU_FETCH_UBWC) && \
test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
@ -290,67 +270,6 @@ enum dpu_vbif {
VBIF_MAX,
};
/**
* DPU HW,Component order color map
*/
enum {
C0_G_Y = 0,
C1_B_Cb = 1,
C2_R_Cr = 2,
C3_ALPHA = 3
};
/**
* enum dpu_plane_type - defines how the color component pixel packing
* @DPU_PLANE_INTERLEAVED : Color components in single plane
* @DPU_PLANE_PLANAR : Color component in separate planes
* @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
*/
enum dpu_plane_type {
DPU_PLANE_INTERLEAVED,
DPU_PLANE_PLANAR,
DPU_PLANE_PSEUDO_PLANAR,
};
/**
* enum dpu_chroma_samp_type - chroma sub-samplng type
* @DPU_CHROMA_RGB : No chroma subsampling
* @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
* @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
* @DPU_CHROMA_420 : 420 subsampling
*/
enum dpu_chroma_samp_type {
DPU_CHROMA_RGB,
DPU_CHROMA_H2V1,
DPU_CHROMA_H1V2,
DPU_CHROMA_420
};
/**
* dpu_fetch_type - Defines How DPU HW fetches data
* @DPU_FETCH_LINEAR : fetch is line by line
* @DPU_FETCH_TILE : fetches data in Z order from a tile
* @DPU_FETCH_UBWC : fetch and decompress data
*/
enum dpu_fetch_type {
DPU_FETCH_LINEAR,
DPU_FETCH_TILE,
DPU_FETCH_UBWC
};
/**
* Value of enum chosen to fit the number of bits
* expected by the HW programming.
*/
enum {
COLOR_ALPHA_1BIT = 0,
COLOR_ALPHA_4BIT = 1,
COLOR_4BIT = 0,
COLOR_5BIT = 1, /* No 5-bit Alpha */
COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
};
/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
@ -370,43 +289,6 @@ enum dpu_3d_blend_mode {
BLEND_3D_MAX
};
/** struct dpu_format - defines the format configuration which
* allows DPU HW to correctly fetch and decode the format
* @base: base msm_format structure containing fourcc code
* @fetch_planes: how the color components are packed in pixel format
* @element: element color ordering
* @bits: element bit widths
* @chroma_sample: chroma sub-samplng type
* @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
* @unpack_tight: 0 for loose, 1 for tight
* @unpack_count: 0 = 1 component, 1 = 2 component
* @bpp: bytes per pixel
* @alpha_enable: whether the format has an alpha channel
* @num_planes: number of planes (including meta data planes)
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
* @flag: usage bit flags
* @tile_width: format tile width
* @tile_height: format tile height
*/
struct dpu_format {
struct msm_format base;
enum dpu_plane_type fetch_planes;
u8 element[DPU_MAX_PLANES];
u8 bits[DPU_MAX_PLANES];
enum dpu_chroma_samp_type chroma_sample;
u8 unpack_align_msb;
u8 unpack_tight;
u8 unpack_count;
u8 bpp;
u8 alpha_enable;
u8 num_planes;
enum dpu_fetch_type fetch_mode;
DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
u16 tile_width;
u16 tile_height;
};
#define to_dpu_format(x) container_of(x, struct dpu_format, base)
/**
* struct dpu_hw_fmt_layout - format information of the source pixel data
* @format: pixel format parameters
@ -419,7 +301,7 @@ struct dpu_format {
* @plane_pitch: pitch of each plane
*/
struct dpu_hw_fmt_layout {
const struct dpu_format *format;
const struct msm_format *format;
uint32_t num_planes;
uint32_t width;
uint32_t height;

40
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
View File

@ -208,7 +208,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
* Setup source pixel format, flip,
*/
static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, u32 flags)
const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
@ -243,20 +243,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = fmt->chroma_sample;
if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
if (chroma_samp == DPU_CHROMA_H2V1)
chroma_samp = DPU_CHROMA_H1V2;
else if (chroma_samp == DPU_CHROMA_H1V2)
chroma_samp = DPU_CHROMA_H2V1;
if (chroma_samp == CHROMA_H2V1)
chroma_samp = CHROMA_H1V2;
else if (chroma_samp == CHROMA_H1V2)
chroma_samp = CHROMA_H2V1;
}
src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
(fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
(fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
(fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
(fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@ -265,12 +265,12 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
(fmt->unpack_tight << 17) |
(fmt->unpack_align_msb << 18) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
if (DPU_FORMAT_IS_UBWC(fmt))
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
@ -297,7 +297,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
break;
case UBWC_4_0:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
}
@ -305,20 +305,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
/* if this is YUV pixel format, enable CSC */
if (DPU_FORMAT_IS_YUV(fmt))
if (MSM_FORMAT_IS_YUV(fmt))
src_format |= BIT(15);
if (DPU_FORMAT_IS_DX(fmt))
if (MSM_FORMAT_IS_DX(fmt))
src_format |= BIT(14);
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
DPU_FORMAT_IS_YUV(fmt));
MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
DPU_FORMAT_IS_YUV(fmt));
MSM_FORMAT_IS_YUV(fmt));
DPU_REG_WRITE(c, format_off, src_format);
DPU_REG_WRITE(c, unpack_pat_off, unpack);
@ -387,7 +387,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
const struct dpu_format *format)
const struct msm_format *format)
{
if (!ctx || !scaler3_cfg)
return;
@ -558,7 +558,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt,
const struct msm_format *fmt,
bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
View File

@ -183,7 +183,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
*/
void (*setup_format)(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, u32 flags);
const struct msm_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
const struct dpu_format *format);
const struct msm_format *format);
/**
* setup_cdp - setup client driven prefetch
@ -288,7 +288,7 @@ struct dpu_hw_sspp_ops {
* @enable: whether the CDP should be enabled for this pipe
*/
void (*setup_cdp)(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt,
const struct msm_format *fmt,
bool enable);
};

14
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
View File

@ -282,7 +282,7 @@ static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
const struct dpu_format *format)
const struct msm_format *format)
{
u32 op_mode = 0;
u32 phase_init, preload, src_y_rgb, src_uv, dst;
@ -293,7 +293,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
op_mode |= BIT(0);
op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
if (format && DPU_FORMAT_IS_YUV(format)) {
if (format && MSM_FORMAT_IS_YUV(format)) {
op_mode |= BIT(12);
op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
}
@ -367,7 +367,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
end:
if (format && !DPU_FORMAT_IS_DX(format))
if (format && !MSM_FORMAT_IS_DX(format))
op_mode |= BIT(14);
if (format && format->alpha_enable) {
@ -522,16 +522,16 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
#define CDP_PRELOAD_AHEAD_64 BIT(3)
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
const struct dpu_format *fmt, bool enable)
const struct msm_format *fmt, bool enable)
{
u32 cdp_cntl = CDP_PRELOAD_AHEAD_64;
if (enable)
cdp_cntl |= CDP_ENABLE;
if (DPU_FORMAT_IS_UBWC(fmt))
if (MSM_FORMAT_IS_UBWC(fmt))
cdp_cntl |= CDP_UBWC_META_ENABLE;
if (DPU_FORMAT_IS_UBWC(fmt) ||
DPU_FORMAT_IS_TILE(fmt))
if (MSM_FORMAT_IS_UBWC(fmt) ||
MSM_FORMAT_IS_TILE(fmt))
cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE;
DPU_REG_WRITE(c, offset, cdp_cntl);

4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
View File

@ -344,14 +344,14 @@ void *dpu_hw_util_get_dir(void);
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
const struct dpu_format *format);
const struct msm_format *format);
void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
u32 csc_reg_off,
const struct dpu_csc_cfg *data, bool csc10);
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
const struct dpu_format *fmt, bool enable);
const struct msm_format *fmt, bool enable);
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
u32 total_fl);

22
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
View File

@ -67,7 +67,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
struct dpu_hw_wb_cfg *data)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
const struct dpu_format *fmt = data->dest.format;
const struct msm_format *fmt = data->dest.format;
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
u32 write_config = 0;
u32 opmode = 0;
@ -76,20 +76,20 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
chroma_samp = fmt->chroma_sample;
dst_format = (chroma_samp << 23) |
(fmt->fetch_planes << 19) |
(fmt->bits[C3_ALPHA] << 6) |
(fmt->bits[C2_R_Cr] << 4) |
(fmt->bits[C1_B_Cb] << 2) |
(fmt->bits[C0_G_Y] << 0);
(fmt->fetch_type << 19) |
(fmt->bpc_a << 6) |
(fmt->bpc_r_cr << 4) |
(fmt->bpc_b_cb << 2) |
(fmt->bpc_g_y << 0);
if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
if (fmt->bpc_a || fmt->alpha_enable) {
dst_format |= BIT(8); /* DSTC3_EN */
if (!fmt->alpha_enable ||
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
dst_format |= BIT(14); /* DST_ALPHA_X */
}
if (DPU_FORMAT_IS_YUV(fmt))
if (MSM_FORMAT_IS_YUV(fmt))
dst_format |= BIT(15);
pattern = (fmt->element[3] << 24) |
@ -97,8 +97,8 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[1] << 8) |
(fmt->element[0] << 0);
dst_format |= (fmt->unpack_align_msb << 18) |
(fmt->unpack_tight << 17) |
dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
@ -149,7 +149,7 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
}
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
const struct dpu_format *fmt,
const struct msm_format *fmt,
bool enable)
{
if (!ctx)

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
View File

@ -46,7 +46,7 @@ struct dpu_hw_wb_ops {
struct dpu_hw_qos_cfg *cfg);
void (*setup_cdp)(struct dpu_hw_wb *ctx,
const struct dpu_format *fmt,
const struct msm_format *fmt,
bool enable);
bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx,

13
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -348,9 +348,18 @@ static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
kfree(dpu_state);
}
static void dpu_kms_global_print_state(struct drm_printer *p,
const struct drm_private_state *state)
{
const struct dpu_global_state *global_state = to_dpu_global_state(state);
dpu_rm_print_state(p, global_state);
}
static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
.atomic_duplicate_state = dpu_kms_global_duplicate_state,
.atomic_destroy_state = dpu_kms_global_destroy_state,
.atomic_print_state = dpu_kms_global_print_state,
};
static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
@ -364,6 +373,9 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
&state->base,
&dpu_kms_global_state_funcs);
state->rm = &dpu_kms->rm;
return 0;
}
@ -970,7 +982,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
.get_format = dpu_get_msm_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS

2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
View File

@ -130,6 +130,8 @@ struct vsync_info {
struct dpu_global_state {
struct drm_private_state base;
struct dpu_rm *rm;
uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0];
uint32_t mixer_to_enc_id[LM_MAX - LM_0];
uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];

91
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@ -113,7 +113,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
* Prefill BW Equation: line src bytes * line_time
*/
static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
const struct dpu_format *fmt,
const struct msm_format *fmt,
const struct drm_display_mode *mode,
struct dpu_sw_pipe_cfg *pipe_cfg)
{
@ -195,7 +195,7 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
enum dpu_qos_lut_usage lut_usage,
const struct dpu_format *fmt, u32 src_width)
const struct msm_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
u32 fixed_buff_size;
@ -214,8 +214,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == DPU_CHROMA_420) {
if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
((src_width + 32) * fmt->bpp);
@ -234,9 +234,9 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
}
}
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
pipe->sspp->idx - SSPP_VIG0,
(char *)&fmt->base.pixel_format,
&fmt->pixel_format,
src_width, total_fl);
return total_fl;
@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_qos_cfg cfg;
@ -260,7 +260,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
else
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
@ -284,26 +284,26 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
pdpu->is_rt_pipe);
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
(fmt) ? fmt->pixel_format : 0,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
pdpu->pipe - SSPP_VIG0,
fmt ? (char *)&fmt->base.pixel_format : NULL,
fmt ? &fmt->pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
(fmt) ? fmt->pixel_format : 0,
(fmt) ? fmt->fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
fmt ? (char *)&fmt->base.pixel_format : NULL,
fmt ? fmt->fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
fmt ? &fmt->pixel_format : NULL,
fmt ? fmt->fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg);
}
@ -425,7 +425,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
const struct dpu_format *fmt,
const struct msm_format *fmt,
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
unsigned int rotation)
{
@ -477,7 +477,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
}
}
if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
&& (src_w == dst_w))
return;
@ -510,11 +510,11 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
}
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt)
const struct msm_format *fmt)
{
const struct dpu_csc_cfg *csc_ptr;
if (!DPU_FORMAT_IS_YUV(fmt))
if (!MSM_FORMAT_IS_YUV(fmt))
return NULL;
if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
@ -526,12 +526,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
}
static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
const struct dpu_format *fmt, bool color_fill,
const struct msm_format *fmt, bool color_fill,
struct dpu_sw_pipe_cfg *pipe_cfg,
unsigned int rotation)
{
struct dpu_hw_sspp *pipe_hw = pipe->sspp;
const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
@ -577,7 +577,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
struct dpu_sw_pipe *pipe,
struct drm_rect *dst_rect,
u32 fill_color,
const struct dpu_format *fmt)
const struct msm_format *fmt)
{
struct dpu_sw_pipe_cfg pipe_cfg;
@ -615,8 +615,9 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
const struct dpu_format *fmt;
const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
struct msm_drm_private *priv = plane->dev->dev_private;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@ -626,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
@ -704,7 +705,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
struct drm_rect src, const struct dpu_format *fmt)
struct drm_rect src, const struct msm_format *fmt)
{
size_t num_formats;
const u32 *supported_formats;
@ -723,8 +724,8 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
supported_formats = sblk->rotation_cfg->rot_format_list;
num_formats = sblk->rotation_cfg->rot_num_formats;
if (!DPU_FORMAT_IS_UBWC(fmt) ||
!dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
if (!MSM_FORMAT_IS_UBWC(fmt) ||
!dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
return -EINVAL;
return 0;
@ -733,15 +734,15 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
const struct dpu_format *fmt,
const struct msm_format *fmt,
const struct drm_display_mode *mode)
{
uint32_t min_src_size;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
if (DPU_FORMAT_IS_YUV(fmt) &&
if (MSM_FORMAT_IS_YUV(fmt) &&
(!pipe->sspp->cap->sblk->scaler_blk.len ||
!pipe->sspp->cap->sblk->csc_blk.len)) {
DPU_DEBUG_PLANE(pdpu,
@ -758,7 +759,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
}
/* valid yuv image */
if (DPU_FORMAT_IS_YUV(fmt) &&
if (MSM_FORMAT_IS_YUV(fmt) &&
(pipe_cfg->src_rect.x1 & 0x1 ||
pipe_cfg->src_rect.y1 & 0x1 ||
drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
@ -798,7 +799,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_sw_pipe *pipe = &pstate->pipe;
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
const struct dpu_format *fmt;
const struct msm_format *fmt;
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
@ -858,7 +859,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -E2BIG;
}
fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
fmt = msm_framebuffer_format(new_plane_state->fb);
max_linewidth = pdpu->catalog->caps->max_linewidth;
@ -870,7 +871,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
* full width is more than max_linewidth, thus each rect is
* wider than allowed.
*/
if (DPU_FORMAT_IS_UBWC(fmt) &&
if (MSM_FORMAT_IS_UBWC(fmt) &&
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
@ -887,7 +888,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
(!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
!test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
DPU_FORMAT_IS_YUV(fmt)) {
MSM_FORMAT_IS_YUV(fmt)) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
@ -945,8 +946,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
{
const struct dpu_format *format =
to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
const struct msm_format *format =
msm_framebuffer_format(pdpu->base.state->fb);
const struct dpu_csc_cfg *csc_ptr;
if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
@ -1017,7 +1018,7 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
const struct dpu_format *fmt,
const struct msm_format *fmt,
int frame_rate,
struct dpu_hw_fmt_layout *layout)
{
@ -1095,8 +1096,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
const struct dpu_format *fmt =
to_dpu_format(msm_framebuffer_format(fb));
const struct msm_format *fmt =
msm_framebuffer_format(fb);
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
@ -1118,9 +1119,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pdpu->is_rt_pipe = is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
crtc->base.id, DRM_RECT_ARG(&state->dst),
(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
drm_mode_vrefresh(&crtc->mode),

56
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
View File

@ -758,3 +758,59 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
return num_blks;
}
static void dpu_rm_print_state_helper(struct drm_printer *p,
struct dpu_hw_blk *blk,
uint32_t mapping)
{
if (!blk)
drm_puts(p, "- ");
else if (!mapping)
drm_puts(p, "# ");
else
drm_printf(p, "%d ", mapping);
}
void dpu_rm_print_state(struct drm_printer *p,
const struct dpu_global_state *global_state)
{
const struct dpu_rm *rm = global_state->rm;
int i;
drm_puts(p, "resource mapping:\n");
drm_puts(p, "\tpingpong=");
for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++)
dpu_rm_print_state_helper(p, rm->pingpong_blks[i],
global_state->pingpong_to_enc_id[i]);
drm_puts(p, "\n");
drm_puts(p, "\tmixer=");
for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++)
dpu_rm_print_state_helper(p, rm->mixer_blks[i],
global_state->mixer_to_enc_id[i]);
drm_puts(p, "\n");
drm_puts(p, "\tctl=");
for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++)
dpu_rm_print_state_helper(p, rm->ctl_blks[i],
global_state->ctl_to_enc_id[i]);
drm_puts(p, "\n");
drm_puts(p, "\tdspp=");
for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++)
dpu_rm_print_state_helper(p, rm->dspp_blks[i],
global_state->dspp_to_enc_id[i]);
drm_puts(p, "\n");
drm_puts(p, "\tdsc=");
for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++)
dpu_rm_print_state_helper(p, rm->dsc_blks[i],
global_state->dsc_to_enc_id[i]);
drm_puts(p, "\n");
drm_puts(p, "\tcdm=");
dpu_rm_print_state_helper(p, rm->cdm_blk,
global_state->cdm_to_enc_id);
drm_puts(p, "\n");
}

8
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
View File

@ -89,6 +89,14 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
struct dpu_global_state *global_state, uint32_t enc_id,
enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
/**
* dpu_rm_print_state - output the RM private state
* @p: DRM printer
* @global_state: global state
*/
void dpu_rm_print_state(struct drm_printer *p,
const struct dpu_global_state *global_state);
/**
* dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
* @rm: DPU Resource Manager handle

1181
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
View File

File diff suppressed because it is too large Load Diff

4
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
View File

@ -182,8 +182,8 @@ static void blend_setup(struct drm_crtc *crtc)
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
int idx = idxs[pipe_id];
if (idx > 0) {
const struct mdp_format *format =
to_mdp_format(msm_framebuffer_format(plane->state->fb));
const struct msm_format *format =
msm_framebuffer_format(plane->state->fb);
alpha[idx-1] = format->alpha_enable;
}
}

1
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
View File

@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit = mdp4_flush_commit,
.wait_flush = mdp4_wait_flush,
.complete_commit = mdp4_complete_commit,
.get_format = mdp_get_format,
.round_pixclk = mdp4_round_pixclk,
.destroy = mdp4_destroy,
},

4
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
View File

@ -44,12 +44,12 @@ struct mdp4_kms {
static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
{
msm_writel(data, mdp4_kms->mmio + reg);
writel(data, mdp4_kms->mmio + reg);
}
static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
{
return msm_readl(mdp4_kms->mmio + reg);
return readl(mdp4_kms->mmio + reg);
}
static inline uint32_t pipe2flush(enum mdp4_pipe pipe)

129
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
View File

@ -20,12 +20,6 @@ struct mdp4_plane {
const char *name;
enum mdp4_pipe pipe;
uint32_t caps;
uint32_t nformats;
uint32_t formats[32];
bool enabled;
};
#define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
@ -59,15 +53,6 @@ static struct mdp4_kms *get_kms(struct drm_plane *plane)
return to_mdp4_kms(to_mdp_kms(priv->kms));
}
static void mdp4_plane_destroy(struct drm_plane *plane)
{
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
drm_plane_cleanup(plane);
kfree(mdp4_plane);
}
/* helper to install properties which are common to planes and crtcs */
static void mdp4_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj)
@ -85,7 +70,6 @@ static int mdp4_plane_set_property(struct drm_plane *plane,
static const struct drm_plane_funcs mdp4_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = mdp4_plane_destroy,
.set_property = mdp4_plane_set_property,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
@ -218,7 +202,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
const struct mdp_format *format;
const struct msm_format *format;
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
@ -241,7 +225,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
format = to_mdp_format(msm_framebuffer_format(fb));
format = msm_framebuffer_format(fb);
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
@ -267,7 +251,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
if (MDP_FORMAT_IS_YUV(format)) {
if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_w > src_w)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_w <= (src_w / 4))
@ -283,7 +267,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
if (MDP_FORMAT_IS_YUV(format)) {
if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_h > src_h)
sel_unit = SCALE_PIXEL_RPT;
@ -316,24 +300,25 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
MDP4_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
MDP4_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
MDP4_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
if (MDP_FORMAT_IS_YUV(format)) {
if (MSM_FORMAT_IS_YUV(format)) {
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
@ -371,37 +356,81 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
static const uint32_t mdp4_rgb_formats[] = {
DRM_FORMAT_ARGB8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
};
static const uint32_t mdp4_rgb_yuv_formats[] = {
DRM_FORMAT_ARGB8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_NV16,
DRM_FORMAT_NV61,
DRM_FORMAT_VYUY,
DRM_FORMAT_UYVY,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_YUV420,
DRM_FORMAT_YVU420,
};
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
{
struct drm_plane *plane = NULL;
struct mdp4_plane *mdp4_plane;
int ret;
enum drm_plane_type type;
uint32_t pipe_caps;
const uint32_t *formats;
size_t nformats;
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
if (!mdp4_plane) {
ret = -ENOMEM;
goto fail;
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
pipe_caps = mdp4_pipe_caps(pipe_id);
if (pipe_supports_yuv(pipe_caps)) {
formats = mdp4_rgb_yuv_formats;
nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
} else {
formats = mdp4_rgb_formats;
nformats = ARRAY_SIZE(mdp4_rgb_formats);
}
mdp4_plane = drmm_universal_plane_alloc(dev, struct mdp4_plane, base,
0xff, &mdp4_plane_funcs,
formats, nformats,
supported_format_modifiers,
type, NULL);
if (IS_ERR(mdp4_plane))
return ERR_CAST(mdp4_plane);
plane = &mdp4_plane->base;
mdp4_plane->pipe = pipe_id;
mdp4_plane->name = pipe_names[pipe_id];
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
ARRAY_SIZE(mdp4_plane->formats),
!pipe_supports_yuv(mdp4_plane->caps));
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
mdp4_plane->formats, mdp4_plane->nformats,
supported_format_modifiers, type, NULL);
if (ret)
goto fail;
drm_plane_helper_add(plane, &mdp4_plane_helper_funcs);
@ -410,10 +439,4 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
drm_plane_enable_fb_damage_clips(plane);
return plane;
fail:
if (plane)
mdp4_plane_destroy(plane);
return ERR_PTR(ret);
}

1979
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
View File

File diff suppressed because it is too large Load Diff

11
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
View File

@ -69,6 +69,16 @@ struct mdp5_mdp_block {
uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */
};
struct mdp5_wb_instance {
int id;
int lm;
};
struct mdp5_wb_block {
MDP5_SUB_BLOCK_DEFINITION;
struct mdp5_wb_instance instances[MAX_BASES];
};
#define MDP5_INTF_NUM_MAX 5
struct mdp5_intf_block {
@ -98,6 +108,7 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block pp;
struct mdp5_sub_block dsc;
struct mdp5_sub_block cdm;
struct mdp5_wb_block wb;
struct mdp5_intf_block intf;
struct mdp5_perf_block perf;

7
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
View File

@ -216,7 +216,7 @@ static void blend_setup(struct drm_crtc *crtc)
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct drm_plane *plane;
struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
const struct mdp_format *format;
const struct msm_format *format;
struct mdp5_hw_mixer *mixer = pipeline->mixer;
uint32_t lm = mixer->lm;
struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
@ -274,7 +274,7 @@ static void blend_setup(struct drm_crtc *crtc)
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
} else if (plane_cnt) {
format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
if (format->alpha_enable)
bg_alpha_enabled = true;
@ -285,8 +285,7 @@ static void blend_setup(struct drm_crtc *crtc)
if (!pstates[i])
continue;
format = to_mdp_format(
msm_framebuffer_format(pstates[i]->base.fb));
format = msm_framebuffer_format(pstates[i]->base.fb);
plane = pstates[i]->base.plane;
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);

1
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
View File

@ -224,7 +224,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.prepare_commit = mdp5_prepare_commit,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
.get_format = mdp_get_format,
.destroy = mdp5_kms_destroy,
},
.set_irqmask = mdp5_set_irqmask,

4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
View File

@ -171,13 +171,13 @@ struct mdp5_encoder {
static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
{
WARN_ON(mdp5_kms->enable_count <= 0);
msm_writel(data, mdp5_kms->mmio + reg);
writel(data, mdp5_kms->mmio + reg);
}
static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
{
WARN_ON(mdp5_kms->enable_count <= 0);
return msm_readl(mdp5_kms->mmio + reg);
return readl(mdp5_kms->mmio + reg);
}
static inline const char *stage2name(enum mdp_mixer_stage_id stage)

125
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
View File

@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
uint32_t nformats;
uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@ -38,15 +35,6 @@ static bool plane_enabled(struct drm_plane_state *state)
return state->visible;
}
static void mdp5_plane_destroy(struct drm_plane *plane)
{
struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
drm_plane_cleanup(plane);
kfree(mdp5_plane);
}
/* helper to install properties which are common to planes and crtcs */
static void mdp5_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj)
@ -138,7 +126,6 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane,
static const struct drm_plane_funcs mdp5_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = mdp5_plane_destroy,
.reset = mdp5_plane_reset,
.atomic_duplicate_state = mdp5_plane_duplicate_state,
.atomic_destroy_state = mdp5_plane_destroy_state,
@ -231,12 +218,12 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
if (plane_enabled(state)) {
unsigned int rotation;
const struct mdp_format *format;
const struct msm_format *format;
struct mdp5_kms *mdp5_kms = get_kms(plane);
uint32_t blkcfg = 0;
format = to_mdp_format(msm_framebuffer_format(state->fb));
if (MDP_FORMAT_IS_YUV(format))
format = msm_framebuffer_format(state->fb);
if (MSM_FORMAT_IS_YUV(format))
caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
if (((state->src_w >> 16) != state->crtc_w) ||
@ -271,8 +258,8 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
new_hwpipe = true;
if (mdp5_kms->smp) {
const struct mdp_format *format =
to_mdp_format(msm_framebuffer_format(state->fb));
const struct msm_format *format =
msm_framebuffer_format(state->fb);
blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
state->src_w >> 16, false);
@ -633,14 +620,14 @@ static int calc_scaley_steps(struct drm_plane *plane,
return 0;
}
static uint32_t get_scale_config(const struct mdp_format *format,
static uint32_t get_scale_config(const struct msm_format *format,
uint32_t src, uint32_t dst, bool horz)
{
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
bool scaling = format->is_yuv ? true : (src != dst);
const struct drm_format_info *info = drm_format_info(format->pixel_format);
bool yuv = MSM_FORMAT_IS_YUV(format);
bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
bool yuv = format->is_yuv;
if (!scaling)
return 0;
@ -664,12 +651,12 @@ static uint32_t get_scale_config(const struct mdp_format *format,
COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
}
static void calc_pixel_ext(const struct mdp_format *format,
static void calc_pixel_ext(const struct msm_format *format,
uint32_t src, uint32_t dst, uint32_t phase_step[2],
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
bool scaling = format->is_yuv ? true : (src != dst);
bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@ -687,11 +674,11 @@ static void calc_pixel_ext(const struct mdp_format *format,
}
static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
const struct mdp_format *format,
const struct msm_format *format,
uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
{
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
const struct drm_format_info *info = drm_format_info(format->pixel_format);
uint32_t lr, tb, req;
int i;
@ -699,7 +686,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
if (format->is_yuv && i == COMP_1_2) {
if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
@ -773,8 +760,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
{
enum mdp5_pipe pipe = hwpipe->pipe;
bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
const struct mdp_format *format =
to_mdp_format(msm_framebuffer_format(fb));
const struct msm_format *format =
msm_framebuffer_format(fb);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
@ -798,21 +785,22 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
(hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
@ -845,7 +833,7 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
}
if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
if (MDP_FORMAT_IS_YUV(format))
if (MSM_FORMAT_IS_YUV(format))
csc_enable(mdp5_kms, pipe,
mdp_get_default_csc_cfg(CSC_YUV2RGB));
else
@ -864,7 +852,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
struct mdp5_kms *mdp5_kms = get_kms(plane);
enum mdp5_pipe pipe = hwpipe->pipe;
struct mdp5_hw_pipe *right_hwpipe;
const struct mdp_format *format;
const struct msm_format *format;
uint32_t nplanes, config = 0;
struct phase_step step = { { 0 } };
struct pixel_ext pe = { { 0 } };
@ -885,8 +873,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
if (WARN_ON(nplanes > pipe2nclients(pipe)))
return -EINVAL;
format = to_mdp_format(msm_framebuffer_format(fb));
pix_format = format->base.pixel_format;
format = msm_framebuffer_format(fb);
pix_format = format->pixel_format;
src_x = src->x1;
src_y = src->y1;
@ -1007,31 +995,48 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
static const uint32_t mdp5_plane_formats[] = {
DRM_FORMAT_ARGB8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
DRM_FORMAT_BGR565,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_NV16,
DRM_FORMAT_NV61,
DRM_FORMAT_VYUY,
DRM_FORMAT_UYVY,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_YUV420,
DRM_FORMAT_YVU420,
};
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
{
struct drm_plane *plane = NULL;
struct mdp5_plane *mdp5_plane;
int ret;
mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
if (!mdp5_plane) {
ret = -ENOMEM;
goto fail;
}
mdp5_plane = drmm_universal_plane_alloc(dev, struct mdp5_plane, base,
0xff, &mdp5_plane_funcs,
mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
NULL, type, NULL);
if (IS_ERR(mdp5_plane))
return ERR_CAST(mdp5_plane);
plane = &mdp5_plane->base;
mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
ARRAY_SIZE(mdp5_plane->formats), false);
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
mdp5_plane->formats, mdp5_plane->nformats,
NULL, type, NULL);
if (ret)
goto fail;
drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
mdp5_plane_install_properties(plane, &plane->base);
@ -1039,10 +1044,4 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
drm_plane_enable_fb_damage_clips(plane);
return plane;
fail:
if (plane)
mdp5_plane_destroy(plane);
return ERR_PTR(ret);
}

4
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
View File

@ -114,10 +114,10 @@ static void set_fifo_thresholds(struct mdp5_smp *smp,
* presumably happens during the dma from scanout buffer).
*/
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
const struct mdp_format *format,
const struct msm_format *format,
u32 width, bool hdecim)
{
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
const struct drm_format_info *info = drm_format_info(format->pixel_format);
struct mdp5_kms *mdp5_kms = get_kms(smp);
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
int i, hsub, nplanes, nlines;

2
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
View File

@ -74,7 +74,7 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
struct mdp5_global_state *global_state);
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
const struct mdp_format *format,
const struct msm_format *format,
u32 width, bool hdecim);
int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,

111
drivers/gpu/drm/msm/disp/mdp_common.xml.h
View File

@ -1,111 +0,0 @@
#ifndef MDP_COMMON_XML
#define MDP_COMMON_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum mdp_chroma_samp_type {
CHROMA_FULL = 0,
CHROMA_H2V1 = 1,
CHROMA_H1V2 = 2,
CHROMA_420 = 3,
};
enum mdp_fetch_type {
MDP_PLANE_INTERLEAVED = 0,
MDP_PLANE_PLANAR = 1,
MDP_PLANE_PSEUDO_PLANAR = 2,
};
enum mdp_mixer_stage_id {
STAGE_UNUSED = 0,
STAGE_BASE = 1,
STAGE0 = 2,
STAGE1 = 3,
STAGE2 = 4,
STAGE3 = 5,
STAGE4 = 6,
STAGE5 = 7,
STAGE6 = 8,
STAGE_MAX = 8,
};
enum mdp_alpha_type {
FG_CONST = 0,
BG_CONST = 1,
FG_PIXEL = 2,
BG_PIXEL = 3,
};
enum mdp_component_type {
COMP_0 = 0,
COMP_1_2 = 1,
COMP_3 = 2,
COMP_MAX = 3,
};
enum mdp_bpc {
BPC1 = 0,
BPC5 = 1,
BPC6 = 2,
BPC8 = 3,
};
enum mdp_bpc_alpha {
BPC1A = 0,
BPC4A = 1,
BPC6A = 2,
BPC8A = 3,
};
#endif /* MDP_COMMON_XML */

630
drivers/gpu/drm/msm/disp/mdp_format.c
View File

@ -62,115 +62,573 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
.base = { .pixel_format = DRM_FORMAT_ ## name }, \
.bpc_a = BPC ## a ## A, \
.bpc_r = BPC ## r, \
.bpc_g = BPC ## g, \
.bpc_b = BPC ## b, \
.unpack = { e0, e1, e2, e3 }, \
.alpha_enable = alpha, \
.unpack_tight = tight, \
.cpp = c, \
.unpack_count = cnt, \
.fetch_type = fp, \
.chroma_sample = cs, \
.is_yuv = yuv, \
#define MDP_TILE_HEIGHT_DEFAULT 1
#define MDP_TILE_HEIGHT_UBWC 4
#define MDP_TILE_HEIGHT_NV12 8
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
bp, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
#define BPC0A 0
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
alpha, bp, flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
/*
* Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
* mdp_get_rgb_formats()'s implementation.
*/
static const struct mdp_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, true, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, true, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
alpha, chroma, count, bp, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = th \
}
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
static const struct msm_format mdp_formats[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA8888,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA8888,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX8888,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB8888,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX8888,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB888,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 3, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR888,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 3, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB565,
0, BPC5, BPC6, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB1555,
BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR1555,
BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA5551,
BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA5551,
BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB1555,
BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR1555,
BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX5551,
BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX5551,
BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB4444,
BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR4444,
BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA4444,
BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA4444,
BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB4444,
BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR4444,
BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX4444,
BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX4444,
BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
PSEUDO_YUV_FMT(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
/* 1 plane YUV */
FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, true, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, true, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
INTERLEAVED_YUV_FMT(VYUY,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
0, BPC8, BPC8, BPC8,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
0, BPC8, BPC8, BPC8,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
/* 3 plane YUV */
FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
PLANAR_YUV_FMT(YUV420,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb, C0_G_Y,
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr, C0_G_Y,
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
};
/*
* Note:
* @rgb_only must be set to true, when requesting
* supported formats for RGB pipes.
* UBWC formats table:
* This table holds the UBWC formats supported.
* If a compression ratio needs to be used for this or any other format,
* the data will be passed by user-space.
*/
uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats,
bool rgb_only)
{
uint32_t i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
const struct mdp_format *f = &formats[i];
static const struct msm_format mdp_formats_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
if (i == max_formats)
break;
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
if (rgb_only && MDP_FORMAT_IS_YUV(f))
break;
/* ARGB8888 and ABGR8888 purposely have the same color
* ordering. The hardware only supports ABGR8888 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
pixel_formats[i] = f->base.pixel_format;
}
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
return i;
}
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
* ordering. The hardware only supports ARGB2101010 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
CHROMA_420, MSM_FORMAT_FLAG_YUV |
MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
CHROMA_420, MSM_FORMAT_FLAG_DX |
MSM_FORMAT_FLAG_YUV |
MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
};
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
const struct msm_format *map = NULL;
ssize_t map_size;
int i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
const struct mdp_format *f = &formats[i];
if (f->base.pixel_format == format)
return &f->base;
switch (modifier) {
case 0:
map = mdp_formats;
map_size = ARRAY_SIZE(mdp_formats);
break;
case DRM_FORMAT_MOD_QCOM_COMPRESSED:
map = mdp_formats_ubwc;
map_size = ARRAY_SIZE(mdp_formats_ubwc);
break;
default:
drm_err(kms->dev, "unsupported format modifier %llX\n", modifier);
return NULL;
}
for (i = 0; i < map_size; i++) {
const struct msm_format *f = &map[i];
if (f->pixel_format == format)
return f;
}
drm_err(kms->dev, "unsupported fmt: %p4cc modifier 0x%llX\n",
&format, modifier);
return NULL;
}

77
drivers/gpu/drm/msm/disp/mdp_format.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*/
#ifndef __MSM_FORMAT_H__
#define __MSM_FORMAT_H__
#include "mdp_common.xml.h"
enum msm_format_flags {
MSM_FORMAT_FLAG_YUV_BIT,
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
/**
* DPU HW,Component order color map
*/
enum {
C0_G_Y = 0,
C1_B_Cb = 1,
C2_R_Cr = 2,
C3_ALPHA = 3
};
/**
* struct msm_format: defines the format configuration
* @pixel_format: format fourcc
* @element: element color ordering
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
* @flags: usage bit flags
* @num_planes: number of planes (including meta data planes)
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
* @tile_height: format tile height
*/
struct msm_format {
uint32_t pixel_format;
enum mdp_bpc bpc_g_y, bpc_b_cb, bpc_r_cr;
enum mdp_bpc_alpha bpc_a;
u8 element[4];
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
u8 unpack_count;
u8 bpp;
unsigned long flags;
u8 num_planes;
enum mdp_fetch_mode fetch_mode;
u16 tile_height;
};
#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
#define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX)
#define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
#define MSM_FORMAT_IS_TILE(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
!((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
#define MSM_FORMAT_IS_UBWC(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
#endif

18
drivers/gpu/drm/msm/disp/mdp_kms.h
View File

@ -11,6 +11,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include "mdp_format.h"
#include "msm_drv.h"
#include "msm_kms.h"
#include "mdp_common.xml.h"
@ -77,23 +78,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
struct mdp_format {
struct msm_format base;
enum mdp_bpc bpc_r, bpc_g, bpc_b;
enum mdp_bpc_alpha bpc_a;
uint8_t unpack[4];
bool alpha_enable, unpack_tight;
uint8_t cpp, unpack_count;
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool is_yuv;
};
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
/* MDP capabilities */
#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */

25
drivers/gpu/drm/msm/dp/dp_audio.c
View File

@ -22,9 +22,7 @@ struct dp_audio_private {
struct platform_device *pdev;
struct drm_device *drm_dev;
struct dp_catalog *catalog;
struct dp_panel *panel;
bool engine_on;
u32 channels;
struct dp_audio dp_audio;
@ -34,11 +32,7 @@ static u32 dp_audio_get_header(struct dp_catalog *catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header)
{
catalog->sdp_type = sdp;
catalog->sdp_header = header;
dp_catalog_audio_get_header(catalog);
return catalog->audio_data;
return dp_catalog_audio_get_header(catalog, sdp, header);
}
static void dp_audio_set_header(struct dp_catalog *catalog,
@ -46,10 +40,7 @@ static void dp_audio_set_header(struct dp_catalog *catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header)
{
catalog->sdp_type = sdp;
catalog->sdp_header = header;
catalog->audio_data = data;
dp_catalog_audio_set_header(catalog);
dp_catalog_audio_set_header(catalog, sdp, header, data);
}
static void dp_audio_stream_sdp(struct dp_audio_private *audio)
@ -319,8 +310,7 @@ static void dp_audio_setup_acr(struct dp_audio_private *audio)
break;
}
catalog->audio_data = select;
dp_catalog_audio_config_acr(catalog);
dp_catalog_audio_config_acr(catalog, select);
}
static void dp_audio_safe_to_exit_level(struct dp_audio_private *audio)
@ -346,18 +336,14 @@ static void dp_audio_safe_to_exit_level(struct dp_audio_private *audio)
break;
}
catalog->audio_data = safe_to_exit_level;
dp_catalog_audio_sfe_level(catalog);
dp_catalog_audio_sfe_level(catalog, safe_to_exit_level);
}
static void dp_audio_enable(struct dp_audio_private *audio, bool enable)
{
struct dp_catalog *catalog = audio->catalog;
catalog->audio_data = enable;
dp_catalog_audio_enable(catalog);
audio->engine_on = enable;
dp_catalog_audio_enable(catalog, enable);
}
static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev)
@ -571,7 +557,6 @@ struct dp_audio *dp_audio_get(struct platform_device *pdev,
}
audio->pdev = pdev;
audio->panel = panel;
audio->catalog = catalog;
dp_audio = &audio->dp_audio;

39
drivers/gpu/drm/msm/dp/dp_aux.c
View File

@ -38,6 +38,7 @@ struct dp_aux_private {
bool no_send_stop;
bool initted;
bool is_edp;
bool enable_xfers;
u32 offset;
u32 segment;
@ -87,8 +88,7 @@ static ssize_t dp_aux_write(struct dp_aux_private *aux,
/* index = 0, write */
if (i == 0)
reg |= DP_AUX_DATA_INDEX_WRITE;
aux->catalog->aux_data = reg;
dp_catalog_aux_write_data(aux->catalog);
dp_catalog_aux_write_data(aux->catalog, reg);
}
dp_catalog_aux_clear_trans(aux->catalog, false);
@ -106,8 +106,7 @@ static ssize_t dp_aux_write(struct dp_aux_private *aux,
}
reg |= DP_AUX_TRANS_CTRL_GO;
aux->catalog->aux_data = reg;
dp_catalog_aux_write_trans(aux->catalog);
dp_catalog_aux_write_trans(aux->catalog, reg);
return len;
}
@ -145,8 +144,7 @@ static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
data |= DP_AUX_DATA_READ; /* read */
aux->catalog->aux_data = data;
dp_catalog_aux_write_data(aux->catalog);
dp_catalog_aux_write_data(aux->catalog, data);
dp = msg->buffer;
@ -305,19 +303,14 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
}
/*
* For eDP it's important to give a reasonably long wait here for HPD
* to be asserted. This is because the panel driver may have _just_
* turned on the panel and then tried to do an AUX transfer. The panel
* driver has no way of knowing when the panel is ready, so it's up
* to us to wait. For DP we never get into this situation so let's
* avoid ever doing the extra long wait for DP.
* If we're using DP and an external display isn't connected then the
* transfer won't succeed. Return right away. If we don't do this we
* can end up with long timeouts if someone tries to access the DP AUX
* character device when no DP device is connected.
*/
if (aux->is_edp) {
ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
if (ret) {
DRM_DEBUG_DP("Panel not ready for aux transactions\n");
goto exit;
}
if (!aux->is_edp && !aux->enable_xfers) {
ret = -ENXIO;
goto exit;
}
dp_aux_update_offset_and_segment(aux, msg);
@ -436,6 +429,14 @@ irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux)
return IRQ_HANDLED;
}
void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled)
{
struct dp_aux_private *aux;
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
aux->enable_xfers = enabled;
}
void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
{
struct dp_aux_private *aux;
@ -513,7 +514,7 @@ static int dp_wait_hpd_asserted(struct drm_dp_aux *dp_aux,
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
pm_runtime_get_sync(aux->dev);
ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_us);
pm_runtime_put_sync(aux->dev);
return ret;

1
drivers/gpu/drm/msm/dp/dp_aux.h
View File

@ -12,6 +12,7 @@
int dp_aux_register(struct drm_dp_aux *dp_aux);
void dp_aux_unregister(struct drm_dp_aux *dp_aux);
irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux);
void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled);
void dp_aux_init(struct drm_dp_aux *dp_aux);
void dp_aux_deinit(struct drm_dp_aux *dp_aux);
void dp_aux_reconfig(struct drm_dp_aux *dp_aux);

71
drivers/gpu/drm/msm/dp/dp_catalog.c
View File

@ -81,7 +81,6 @@ struct dp_catalog_private {
struct dss_io_data io;
u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
struct dp_catalog dp_catalog;
u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
};
void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
@ -170,21 +169,21 @@ u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog)
return dp_read_aux(catalog, REG_DP_AUX_DATA);
}
int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog)
int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
dp_write_aux(catalog, REG_DP_AUX_DATA, dp_catalog->aux_data);
dp_write_aux(catalog, REG_DP_AUX_DATA, data);
return 0;
}
int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog)
int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, dp_catalog->aux_data);
dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data);
return 0;
}
@ -263,17 +262,18 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable)
dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
}
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog)
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog,
unsigned long wait_us)
{
u32 state;
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
/* poll for hpd connected status every 2ms and timeout after 500ms */
/* poll for hpd connected status every 2ms and timeout after wait_us */
return readl_poll_timeout(catalog->io.aux.base +
REG_DP_DP_HPD_INT_STATUS,
state, state & DP_DP_HPD_STATE_STATUS_CONNECTED,
2000, 500000);
min(wait_us, 2000), wait_us);
}
static void dump_regs(void __iomem *base, int len)
@ -469,7 +469,7 @@ void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
u32 rate, u32 stream_rate_khz,
bool fixed_nvid, bool is_ycbcr_420)
bool is_ycbcr_420)
{
u32 pixel_m, pixel_n;
u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
@ -881,19 +881,17 @@ u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog)
}
/* panel related catalog functions */
int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total,
u32 sync_start, u32 width_blanking, u32 dp_active)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
u32 reg;
dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
dp_catalog->total);
dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC,
dp_catalog->sync_start);
dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
dp_catalog->width_blanking);
dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total);
dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);
dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);
dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_active);
reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
@ -1162,34 +1160,28 @@ struct dp_catalog *dp_catalog_get(struct device *dev)
return &catalog->dp_catalog;
}
void dp_catalog_audio_get_header(struct dp_catalog *dp_catalog)
u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header)
{
struct dp_catalog_private *catalog;
u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
enum dp_catalog_audio_sdp_type sdp;
enum dp_catalog_audio_header_type header;
if (!dp_catalog)
return;
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
sdp_map = catalog->audio_map;
sdp = dp_catalog->sdp_type;
header = dp_catalog->sdp_header;
dp_catalog->audio_data = dp_read_link(catalog,
sdp_map[sdp][header]);
return dp_read_link(catalog, sdp_map[sdp][header]);
}
void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog)
void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header,
u32 data)
{
struct dp_catalog_private *catalog;
u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
enum dp_catalog_audio_sdp_type sdp;
enum dp_catalog_audio_header_type header;
u32 data;
if (!dp_catalog)
return;
@ -1198,17 +1190,14 @@ void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog)
struct dp_catalog_private, dp_catalog);
sdp_map = catalog->audio_map;
sdp = dp_catalog->sdp_type;
header = dp_catalog->sdp_header;
data = dp_catalog->audio_data;
dp_write_link(catalog, sdp_map[sdp][header], data);
}
void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog, u32 select)
{
struct dp_catalog_private *catalog;
u32 acr_ctrl, select;
u32 acr_ctrl;
if (!dp_catalog)
return;
@ -1216,7 +1205,6 @@ void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
select = dp_catalog->audio_data;
acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n",
@ -1225,10 +1213,9 @@ void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
}
void dp_catalog_audio_enable(struct dp_catalog *dp_catalog)
void dp_catalog_audio_enable(struct dp_catalog *dp_catalog, bool enable)
{
struct dp_catalog_private *catalog;
bool enable;
u32 audio_ctrl;
if (!dp_catalog)
@ -1237,7 +1224,6 @@ void dp_catalog_audio_enable(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
enable = !!dp_catalog->audio_data;
audio_ctrl = dp_read_link(catalog, MMSS_DP_AUDIO_CFG);
if (enable)
@ -1332,10 +1318,10 @@ void dp_catalog_audio_init(struct dp_catalog *dp_catalog)
catalog->audio_map = sdp_map;
}
void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog)
void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog, u32 safe_to_exit_level)
{
struct dp_catalog_private *catalog;
u32 mainlink_levels, safe_to_exit_level;
u32 mainlink_levels;
if (!dp_catalog)
return;
@ -1343,7 +1329,6 @@ void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
safe_to_exit_level = dp_catalog->audio_data;
mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS);
mainlink_levels &= 0xFE0;
mainlink_levels |= safe_to_exit_level;

52
drivers/gpu/drm/msm/dp/dp_catalog.h
View File

@ -28,26 +28,9 @@
#define DP_INTR_FRAME_END BIT(6)
#define DP_INTR_CRC_UPDATED BIT(9)
#define DP_AUX_CFG_MAX_VALUE_CNT 3
#define DP_HW_VERSION_1_0 0x10000000
#define DP_HW_VERSION_1_2 0x10020000
/* PHY AUX config registers */
enum dp_phy_aux_config_type {
PHY_AUX_CFG0,
PHY_AUX_CFG1,
PHY_AUX_CFG2,
PHY_AUX_CFG3,
PHY_AUX_CFG4,
PHY_AUX_CFG5,
PHY_AUX_CFG6,
PHY_AUX_CFG7,
PHY_AUX_CFG8,
PHY_AUX_CFG9,
PHY_AUX_CFG_MAX,
};
enum dp_catalog_audio_sdp_type {
DP_AUDIO_SDP_STREAM,
DP_AUDIO_SDP_TIMESTAMP,
@ -65,14 +48,6 @@ enum dp_catalog_audio_header_type {
};
struct dp_catalog {
u32 aux_data;
u32 total;
u32 sync_start;
u32 width_blanking;
u32 dp_active;
enum dp_catalog_audio_sdp_type sdp_type;
enum dp_catalog_audio_header_type sdp_header;
u32 audio_data;
bool wide_bus_en;
};
@ -81,13 +56,14 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d
/* AUX APIs */
u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog);
int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data);
int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data);
int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read);
int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog);
void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog);
int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog,
unsigned long wait_us);
u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
/* DP Controller APIs */
@ -99,7 +75,7 @@ void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool ena
void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420);
u32 stream_rate_khz, bool is_ycbcr_420);
int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);
u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);
@ -124,7 +100,8 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog);
/* DP Panel APIs */
int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog);
int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total,
u32 sync_start, u32 width_blanking, u32 dp_active);
void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp);
void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog);
void dp_catalog_dump_regs(struct dp_catalog *dp_catalog);
@ -135,12 +112,17 @@ void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog);
struct dp_catalog *dp_catalog_get(struct device *dev);
/* DP Audio APIs */
void dp_catalog_audio_get_header(struct dp_catalog *catalog);
void dp_catalog_audio_set_header(struct dp_catalog *catalog);
void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
void dp_catalog_audio_enable(struct dp_catalog *catalog);
u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header);
void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header,
u32 data);
void dp_catalog_audio_config_acr(struct dp_catalog *catalog, u32 select);
void dp_catalog_audio_enable(struct dp_catalog *catalog, bool enable);
void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
void dp_catalog_audio_init(struct dp_catalog *catalog);
void dp_catalog_audio_sfe_level(struct dp_catalog *catalog);
void dp_catalog_audio_sfe_level(struct dp_catalog *catalog, u32 safe_to_exit_level);
#endif /* _DP_CATALOG_H_ */

23
drivers/gpu/drm/msm/dp/dp_ctrl.c
View File

@ -1052,14 +1052,14 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
if (ret)
return ret;
if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
if (voltage_swing_level >= DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(ctrl->drm_dev,
"max. voltage swing level reached %d\n",
voltage_swing_level);
max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
}
if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
if (pre_emphasis_level >= DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(ctrl->drm_dev,
"max. pre-emphasis level reached %d\n",
pre_emphasis_level);
@ -1150,7 +1150,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
}
if (ctrl->link->phy_params.v_level >=
DP_TRAIN_VOLTAGE_SWING_MAX) {
DP_TRAIN_LEVEL_MAX) {
DRM_ERROR_RATELIMITED("max v_level reached\n");
return -EAGAIN;
}
@ -1566,21 +1566,6 @@ void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
phy, phy->init_count, phy->power_count);
}
static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
{
const u8 *dpcd = ctrl->panel->dpcd;
/*
* For better interop experience, used a fixed NVID=0x8000
* whenever connected to a VGA dongle downstream.
*/
if (drm_dp_is_branch(dpcd))
return (drm_dp_has_quirk(&ctrl->panel->desc,
DP_DPCD_QUIRK_CONSTANT_N));
return false;
}
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
struct phy *phy = ctrl->phy;
@ -2022,7 +2007,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
dp_catalog_ctrl_config_msa(ctrl->catalog,
ctrl->link->link_params.rate,
pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl),
pixel_rate_orig,
ctrl->panel->dp_mode.out_fmt_is_yuv_420);
dp_ctrl_setup_tr_unit(ctrl);

1
drivers/gpu/drm/msm/dp/dp_ctrl.h
View File

@ -12,7 +12,6 @@
#include "dp_catalog.h"
struct dp_ctrl {
atomic_t aborted;
bool wide_bus_en;
};

61
drivers/gpu/drm/msm/dp/dp_debug.c
View File

@ -21,8 +21,6 @@ struct dp_debug_private {
struct dp_link *link;
struct dp_panel *panel;
struct drm_connector *connector;
struct dp_debug dp_debug;
};
static int dp_debug_show(struct seq_file *seq, void *p)
@ -199,10 +197,24 @@ static const struct file_operations test_active_fops = {
.write = dp_test_active_write
};
static void dp_debug_init(struct dp_debug *dp_debug, struct dentry *root, bool is_edp)
int dp_debug_init(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root, bool is_edp)
{
struct dp_debug_private *debug = container_of(dp_debug,
struct dp_debug_private, dp_debug);
struct dp_debug_private *debug;
if (!dev || !panel || !link) {
DRM_ERROR("invalid input\n");
return -EINVAL;
}
debug = devm_kzalloc(dev, sizeof(*debug), GFP_KERNEL);
if (!debug)
return -ENOMEM;
debug->link = link;
debug->panel = panel;
debugfs_create_file("dp_debug", 0444, root,
debug, &dp_debug_fops);
@ -220,41 +232,6 @@ static void dp_debug_init(struct dp_debug *dp_debug, struct dentry *root, bool i
root,
debug, &dp_test_type_fops);
}
}
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root, bool is_edp)
{
struct dp_debug_private *debug;
struct dp_debug *dp_debug;
int rc;
if (!dev || !panel || !link) {
DRM_ERROR("invalid input\n");
rc = -EINVAL;
goto error;
}
debug = devm_kzalloc(dev, sizeof(*debug), GFP_KERNEL);
if (!debug) {
rc = -ENOMEM;
goto error;
}
debug->dp_debug.debug_en = false;
debug->link = link;
debug->panel = panel;
dp_debug = &debug->dp_debug;
dp_debug->vdisplay = 0;
dp_debug->hdisplay = 0;
dp_debug->vrefresh = 0;
dp_debug_init(dp_debug, root, is_edp);
return dp_debug;
error:
return ERR_PTR(rc);
return 0;
}

38
drivers/gpu/drm/msm/dp/dp_debug.h
View File

@ -9,22 +9,6 @@
#include "dp_panel.h"
#include "dp_link.h"
/**
* struct dp_debug
* @debug_en: specifies whether debug mode enabled
* @vdisplay: used to filter out vdisplay value
* @hdisplay: used to filter out hdisplay value
* @vrefresh: used to filter out vrefresh value
* @tpg_state: specifies whether tpg feature is enabled
*/
struct dp_debug {
bool debug_en;
int aspect_ratio;
int vdisplay;
int hdisplay;
int vrefresh;
};
#if defined(CONFIG_DEBUG_FS)
/**
@ -41,22 +25,22 @@ struct dp_debug {
* This function sets up the debug module and provides a way
* for debugfs input to be communicated with existing modules
*/
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root,
bool is_edp);
int dp_debug_init(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root,
bool is_edp);
#else
static inline
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root,
bool is_edp)
int dp_debug_init(struct device *dev, struct dp_panel *panel,
struct dp_link *link,
struct drm_connector *connector,
struct dentry *root,
bool is_edp)
{
return ERR_PTR(-EINVAL);
return -EINVAL;
}
#endif /* defined(CONFIG_DEBUG_FS) */

105
drivers/gpu/drm/msm/dp/dp_display.c
View File

@ -74,7 +74,6 @@ struct dp_event {
};
struct dp_display_private {
char *name;
int irq;
unsigned int id;
@ -82,18 +81,15 @@ struct dp_display_private {
/* state variables */
bool core_initialized;
bool phy_initialized;
bool hpd_irq_on;
bool audio_supported;
struct drm_device *drm_dev;
struct dentry *root;
struct dp_catalog *catalog;
struct drm_dp_aux *aux;
struct dp_link *link;
struct dp_panel *panel;
struct dp_ctrl *ctrl;
struct dp_debug *debug;
struct dp_display_mode dp_mode;
struct msm_dp dp_display;
@ -119,55 +115,49 @@ struct dp_display_private {
struct msm_dp_desc {
phys_addr_t io_start;
unsigned int id;
unsigned int connector_type;
bool wide_bus_supported;
};
static const struct msm_dp_desc sc7180_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0 },
{}
};
static const struct msm_dp_desc sc7280_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
{}
};
static const struct msm_dp_desc sc8180x_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
{ .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP },
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0 },
{ .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1 },
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2 },
{}
};
static const struct msm_dp_desc sc8280xp_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{ .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
{}
};
static const struct msm_dp_desc sc8280xp_edp_descs[] = {
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
{ .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
{ .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
{}
};
static const struct msm_dp_desc sm8350_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
{ .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
{ .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
{ .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
{ .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
{ .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
{}
};
static const struct msm_dp_desc sm8650_dp_descs[] = {
{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0 },
{}
};
static const struct msm_dp_desc x1e80100_dp_descs[] = {
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
{ .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
{ .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
{ .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
{}
};
@ -178,10 +168,11 @@ static const struct of_device_id dp_dt_match[] = {
{ .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs },
{ .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs },
{ .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs },
{ .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_edp_descs },
{ .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_dp_descs },
{ .compatible = "qcom,sdm845-dp", .data = &sc7180_dp_descs },
{ .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_descs },
{ .compatible = "qcom,sm8350-dp", .data = &sc7180_dp_descs },
{ .compatible = "qcom,sm8650-dp", .data = &sm8650_dp_descs },
{ .compatible = "qcom,x1e80100-dp", .data = &x1e80100_dp_descs },
{}
};
@ -555,6 +546,8 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)
int ret;
struct platform_device *pdev = dp->dp_display.pdev;
dp_aux_enable_xfers(dp->aux, true);
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
@ -620,6 +613,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)
u32 state;
struct platform_device *pdev = dp->dp_display.pdev;
dp_aux_enable_xfers(dp->aux, false);
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
@ -728,6 +723,14 @@ static int dp_init_sub_modules(struct dp_display_private *dp)
if (IS_ERR(phy))
return PTR_ERR(phy);
rc = phy_set_mode_ext(phy, PHY_MODE_DP,
dp->dp_display.is_edp ? PHY_SUBMODE_EDP : PHY_SUBMODE_DP);
if (rc) {
DRM_ERROR("failed to set phy submode, rc = %d\n", rc);
dp->catalog = NULL;
goto error;
}
dp->catalog = dp_catalog_get(dev);
if (IS_ERR(dp->catalog)) {
rc = PTR_ERR(dp->catalog);
@ -803,7 +806,6 @@ static int dp_display_set_mode(struct msm_dp *dp_display,
drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode);
dp->panel->dp_mode.bpp = mode->bpp;
dp->panel->dp_mode.capabilities = mode->capabilities;
dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420;
dp_panel_init_panel_info(dp->panel);
return 0;
@ -1243,6 +1245,25 @@ static int dp_auxbus_done_probe(struct drm_dp_aux *aux)
return dp_display_probe_tail(aux->dev);
}
static int dp_display_get_connector_type(struct platform_device *pdev,
const struct msm_dp_desc *desc)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *aux_bus = of_get_child_by_name(node, "aux-bus");
struct device_node *panel = of_get_child_by_name(aux_bus, "panel");
int connector_type;
if (panel)
connector_type = DRM_MODE_CONNECTOR_eDP;
else
connector_type = DRM_MODE_SUBCONNECTOR_DisplayPort;
of_node_put(panel);
of_node_put(aux_bus);
return connector_type;
}
static int dp_display_probe(struct platform_device *pdev)
{
int rc = 0;
@ -1263,9 +1284,8 @@ static int dp_display_probe(struct platform_device *pdev)
return -EINVAL;
dp->dp_display.pdev = pdev;
dp->name = "drm_dp";
dp->id = desc->id;
dp->dp_display.connector_type = desc->connector_type;
dp->dp_display.connector_type = dp_display_get_connector_type(pdev, desc);
dp->wide_bus_supported = desc->wide_bus_supported;
dp->dp_display.is_edp =
(dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP);
@ -1433,14 +1453,9 @@ void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, boo
dp = container_of(dp_display, struct dp_display_private, dp_display);
dev = &dp->dp_display.pdev->dev;
dp->debug = dp_debug_get(dev, dp->panel,
dp->link, dp->dp_display.connector,
root, is_edp);
if (IS_ERR(dp->debug)) {
rc = PTR_ERR(dp->debug);
rc = dp_debug_init(dev, dp->panel, dp->link, dp->dp_display.connector, root, is_edp);
if (rc)
DRM_ERROR("failed to initialize debug, rc = %d\n", rc);
dp->debug = NULL;
}
}
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,

3
drivers/gpu/drm/msm/dp/dp_display.h
View File

@ -16,7 +16,6 @@ struct msm_dp {
struct drm_device *drm_dev;
struct platform_device *pdev;
struct device *codec_dev;
struct drm_bridge *bridge;
struct drm_connector *connector;
struct drm_bridge *next_bridge;
bool link_ready;
@ -28,8 +27,6 @@ struct msm_dp {
hdmi_codec_plugged_cb plugged_cb;
bool wide_bus_en;
struct dp_audio *dp_audio;
bool psr_supported;
};

2
drivers/gpu/drm/msm/dp/dp_drm.c
View File

@ -347,8 +347,6 @@ int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
}
}
dp_display->bridge = bridge;
return 0;
}

26
drivers/gpu/drm/msm/dp/dp_link.c
View File

@ -36,7 +36,6 @@ struct dp_link_request {
struct dp_link_private {
u32 prev_sink_count;
struct device *dev;
struct drm_device *drm_dev;
struct drm_dp_aux *aux;
struct dp_link dp_link;
@ -804,8 +803,6 @@ int dp_link_psm_config(struct dp_link *dp_link,
if (ret)
DRM_ERROR("Failed to %s low power mode\n", enable ?
"enter" : "exit");
else
dp_link->psm_enabled = enable;
mutex_unlock(&link->psm_mutex);
return ret;
@ -1109,6 +1106,7 @@ int dp_link_get_colorimetry_config(struct dp_link *dp_link)
int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status)
{
int i;
u8 max_p_level;
int v_max = 0, p_max = 0;
struct dp_link_private *link;
@ -1140,30 +1138,29 @@ int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status)
* Adjust the voltage swing and pre-emphasis level combination to within
* the allowable range.
*/
if (dp_link->phy_params.v_level > DP_TRAIN_VOLTAGE_SWING_MAX) {
if (dp_link->phy_params.v_level > DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(link->drm_dev,
"Requested vSwingLevel=%d, change to %d\n",
dp_link->phy_params.v_level,
DP_TRAIN_VOLTAGE_SWING_MAX);
dp_link->phy_params.v_level = DP_TRAIN_VOLTAGE_SWING_MAX;
DP_TRAIN_LEVEL_MAX);
dp_link->phy_params.v_level = DP_TRAIN_LEVEL_MAX;
}
if (dp_link->phy_params.p_level > DP_TRAIN_PRE_EMPHASIS_MAX) {
if (dp_link->phy_params.p_level > DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(link->drm_dev,
"Requested preEmphasisLevel=%d, change to %d\n",
dp_link->phy_params.p_level,
DP_TRAIN_PRE_EMPHASIS_MAX);
dp_link->phy_params.p_level = DP_TRAIN_PRE_EMPHASIS_MAX;
DP_TRAIN_LEVEL_MAX);
dp_link->phy_params.p_level = DP_TRAIN_LEVEL_MAX;
}
if ((dp_link->phy_params.p_level > DP_TRAIN_PRE_EMPHASIS_LVL_1)
&& (dp_link->phy_params.v_level ==
DP_TRAIN_VOLTAGE_SWING_LVL_2)) {
max_p_level = DP_TRAIN_LEVEL_MAX - dp_link->phy_params.v_level;
if (dp_link->phy_params.p_level > max_p_level) {
drm_dbg_dp(link->drm_dev,
"Requested preEmphasisLevel=%d, change to %d\n",
dp_link->phy_params.p_level,
DP_TRAIN_PRE_EMPHASIS_LVL_1);
dp_link->phy_params.p_level = DP_TRAIN_PRE_EMPHASIS_LVL_1;
max_p_level);
dp_link->phy_params.p_level = max_p_level;
}
drm_dbg_dp(link->drm_dev, "adjusted: v_level=%d, p_level=%d\n",
@ -1226,7 +1223,6 @@ struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux)
if (!link)
return ERR_PTR(-ENOMEM);
link->dev = dev;
link->aux = aux;
mutex_init(&link->psm_mutex);

15
drivers/gpu/drm/msm/dp/dp_link.h
View File

@ -19,19 +19,7 @@ struct dp_link_info {
unsigned long capabilities;
};
enum dp_link_voltage_level {
DP_TRAIN_VOLTAGE_SWING_LVL_0 = 0,
DP_TRAIN_VOLTAGE_SWING_LVL_1 = 1,
DP_TRAIN_VOLTAGE_SWING_LVL_2 = 2,
DP_TRAIN_VOLTAGE_SWING_MAX = DP_TRAIN_VOLTAGE_SWING_LVL_2,
};
enum dp_link_preemaphasis_level {
DP_TRAIN_PRE_EMPHASIS_LVL_0 = 0,
DP_TRAIN_PRE_EMPHASIS_LVL_1 = 1,
DP_TRAIN_PRE_EMPHASIS_LVL_2 = 2,
DP_TRAIN_PRE_EMPHASIS_MAX = DP_TRAIN_PRE_EMPHASIS_LVL_2,
};
#define DP_TRAIN_LEVEL_MAX 3
struct dp_link_test_video {
u32 test_video_pattern;
@ -74,7 +62,6 @@ struct dp_link_phy_params {
struct dp_link {
u32 sink_request;
u32 test_response;
bool psm_enabled;
u8 sink_count;
struct dp_link_test_video test_video;

14
drivers/gpu/drm/msm/dp/dp_panel.c
View File

@ -353,6 +353,10 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
struct dp_catalog *catalog;
struct dp_panel_private *panel;
struct drm_display_mode *drm_mode;
u32 width_blanking;
u32 sync_start;
u32 dp_active;
u32 total;
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
catalog = panel->catalog;
@ -376,13 +380,13 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
data <<= 16;
data |= total_hor;
catalog->total = data;
total = data;
data = (drm_mode->vtotal - drm_mode->vsync_start);
data <<= 16;
data |= (drm_mode->htotal - drm_mode->hsync_start);
catalog->sync_start = data;
sync_start = data;
data = drm_mode->vsync_end - drm_mode->vsync_start;
data <<= 16;
@ -390,15 +394,15 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
data |= drm_mode->hsync_end - drm_mode->hsync_start;
data |= (panel->dp_panel.dp_mode.h_active_low << 15);
catalog->width_blanking = data;
width_blanking = data;
data = drm_mode->vdisplay;
data <<= 16;
data |= drm_mode->hdisplay;
catalog->dp_active = data;
dp_active = data;
dp_catalog_panel_timing_cfg(catalog);
dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blanking, dp_active);
if (dp_panel->dp_mode.out_fmt_is_yuv_420)
dp_panel_setup_vsc_sdp_yuv_420(dp_panel);

3
drivers/gpu/drm/msm/dp/dp_panel.h
View File

@ -15,7 +15,6 @@ struct edid;
struct dp_display_mode {
struct drm_display_mode drm_mode;
u32 capabilities;
u32 bpp;
u32 h_active_low;
u32 v_active_low;
@ -40,7 +39,6 @@ struct dp_panel {
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
struct dp_link_info link_info;
struct drm_dp_desc desc;
struct edid *edid;
struct drm_connector *connector;
struct dp_display_mode dp_mode;
@ -48,7 +46,6 @@ struct dp_panel {
bool video_test;
bool vsc_sdp_supported;
u32 vic;
u32 max_dp_lanes;
u32 max_dp_link_rate;

26
drivers/gpu/drm/msm/dsi/dsi.c
View File

@ -120,6 +120,22 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
struct msm_drm_private *priv = dev_get_drvdata(master);
struct msm_dsi *msm_dsi = dev_get_drvdata(dev);
/*
* Next bridge doesn't exist for the secondary DSI host in a bonded
* pair.
*/
if (!msm_dsi_is_bonded_dsi(msm_dsi) ||
msm_dsi_is_master_dsi(msm_dsi)) {
struct drm_bridge *ext_bridge;
ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev,
msm_dsi->pdev->dev.of_node, 1, 0);
if (IS_ERR(ext_bridge))
return PTR_ERR(ext_bridge);
msm_dsi->next_bridge = ext_bridge;
}
priv->dsi[msm_dsi->id] = msm_dsi;
return 0;
@ -216,7 +232,6 @@ void __exit msm_dsi_unregister(void)
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
struct drm_encoder *encoder)
{
struct drm_bridge *bridge;
int ret;
msm_dsi->dev = dev;
@ -236,14 +251,7 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
return 0;
}
bridge = msm_dsi_manager_bridge_init(msm_dsi, encoder);
if (IS_ERR(bridge)) {
ret = PTR_ERR(bridge);
DRM_DEV_ERROR(dev->dev, "failed to create dsi bridge: %d\n", ret);
return ret;
}
ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id, bridge);
ret = msm_dsi_manager_connector_init(msm_dsi, encoder);
if (ret) {
DRM_DEV_ERROR(dev->dev,
"failed to create dsi connector: %d\n", ret);

7
drivers/gpu/drm/msm/dsi/dsi.h
View File

@ -38,6 +38,8 @@ struct msm_dsi {
struct mipi_dsi_host *host;
struct msm_dsi_phy *phy;
struct drm_bridge *next_bridge;
struct device *phy_dev;
bool phy_enabled;
@ -45,9 +47,8 @@ struct msm_dsi {
};
/* dsi manager */
struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
struct drm_encoder *encoder);
int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge);
int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi,
struct drm_encoder *encoder);
int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);

790
drivers/gpu/drm/msm/dsi/dsi.xml.h
View File

@ -1,790 +0,0 @@
#ifndef DSI_XML
#define DSI_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum dsi_traffic_mode {
NON_BURST_SYNCH_PULSE = 0,
NON_BURST_SYNCH_EVENT = 1,
BURST_MODE = 2,
};
enum dsi_vid_dst_format {
VID_DST_FORMAT_RGB565 = 0,
VID_DST_FORMAT_RGB666 = 1,
VID_DST_FORMAT_RGB666_LOOSE = 2,
VID_DST_FORMAT_RGB888 = 3,
};
enum dsi_rgb_swap {
SWAP_RGB = 0,
SWAP_RBG = 1,
SWAP_BGR = 2,
SWAP_BRG = 3,
SWAP_GRB = 4,
SWAP_GBR = 5,
};
enum dsi_cmd_trigger {
TRIGGER_NONE = 0,
TRIGGER_SEOF = 1,
TRIGGER_TE = 2,
TRIGGER_SW = 4,
TRIGGER_SW_SEOF = 5,
TRIGGER_SW_TE = 6,
};
enum dsi_cmd_dst_format {
CMD_DST_FORMAT_RGB111 = 0,
CMD_DST_FORMAT_RGB332 = 3,
CMD_DST_FORMAT_RGB444 = 4,
CMD_DST_FORMAT_RGB565 = 6,
CMD_DST_FORMAT_RGB666 = 7,
CMD_DST_FORMAT_RGB888 = 8,
};
enum dsi_lane_swap {
LANE_SWAP_0123 = 0,
LANE_SWAP_3012 = 1,
LANE_SWAP_2301 = 2,
LANE_SWAP_1230 = 3,
LANE_SWAP_0321 = 4,
LANE_SWAP_1032 = 5,
LANE_SWAP_2103 = 6,
LANE_SWAP_3210 = 7,
};
enum video_config_bpp {
VIDEO_CONFIG_18BPP = 0,
VIDEO_CONFIG_24BPP = 1,
};
enum video_pattern_sel {
VID_PRBS = 0,
VID_INCREMENTAL = 1,
VID_FIXED = 2,
VID_MDSS_GENERAL_PATTERN = 3,
};
enum cmd_mdp_stream0_pattern_sel {
CMD_MDP_PRBS = 0,
CMD_MDP_INCREMENTAL = 1,
CMD_MDP_FIXED = 2,
CMD_MDP_MDSS_GENERAL_PATTERN = 3,
};
enum cmd_dma_pattern_sel {
CMD_DMA_PRBS = 0,
CMD_DMA_INCREMENTAL = 1,
CMD_DMA_FIXED = 2,
CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3,
};
#define DSI_IRQ_CMD_DMA_DONE 0x00000001
#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
#define DSI_IRQ_CMD_MDP_DONE 0x00000100
#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
#define DSI_IRQ_VIDEO_DONE 0x00010000
#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
#define DSI_IRQ_BTA_DONE 0x00100000
#define DSI_IRQ_MASK_BTA_DONE 0x00200000
#define DSI_IRQ_ERROR 0x01000000
#define DSI_IRQ_MASK_ERROR 0x02000000
#define REG_DSI_6G_HW_VERSION 0x00000000
#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
{
return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
}
#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
#define DSI_6G_HW_VERSION_MINOR__SHIFT 16
static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
{
return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
}
#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
#define DSI_6G_HW_VERSION_STEP__SHIFT 0
static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
{
return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
}
#define REG_DSI_CTRL 0x00000000
#define DSI_CTRL_ENABLE 0x00000001
#define DSI_CTRL_VID_MODE_EN 0x00000002
#define DSI_CTRL_CMD_MODE_EN 0x00000004
#define DSI_CTRL_LANE0 0x00000010
#define DSI_CTRL_LANE1 0x00000020
#define DSI_CTRL_LANE2 0x00000040
#define DSI_CTRL_LANE3 0x00000080
#define DSI_CTRL_CLK_EN 0x00000100
#define DSI_CTRL_ECC_CHECK 0x00100000
#define DSI_CTRL_CRC_CHECK 0x01000000
#define REG_DSI_STATUS0 0x00000004
#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
#define DSI_STATUS0_DSI_BUSY 0x00000010
#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
#define REG_DSI_FIFO_STATUS 0x00000008
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
#define REG_DSI_VID_CFG0 0x0000000c
#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
{
return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
}
#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
{
return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
}
#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
{
return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
}
#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
#define REG_DSI_VID_CFG1 0x0000001c
#define DSI_VID_CFG1_R_SEL 0x00000001
#define DSI_VID_CFG1_G_SEL 0x00000010
#define DSI_VID_CFG1_B_SEL 0x00000100
#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
}
#define REG_DSI_ACTIVE_H 0x00000020
#define DSI_ACTIVE_H_START__MASK 0x00000fff
#define DSI_ACTIVE_H_START__SHIFT 0
static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
{
return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
}
#define DSI_ACTIVE_H_END__MASK 0x0fff0000
#define DSI_ACTIVE_H_END__SHIFT 16
static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
{
return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
}
#define REG_DSI_ACTIVE_V 0x00000024
#define DSI_ACTIVE_V_START__MASK 0x00000fff
#define DSI_ACTIVE_V_START__SHIFT 0
static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
{
return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
}
#define DSI_ACTIVE_V_END__MASK 0x0fff0000
#define DSI_ACTIVE_V_END__SHIFT 16
static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
{
return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
}
#define REG_DSI_TOTAL 0x00000028
#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
#define DSI_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
}
#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
#define DSI_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
{
return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
}
#define REG_DSI_ACTIVE_HSYNC 0x0000002c
#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
#define DSI_ACTIVE_HSYNC_START__SHIFT 0
static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
{
return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
}
#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
#define DSI_ACTIVE_HSYNC_END__SHIFT 16
static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
{
return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
}
#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
{
return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
}
#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
{
return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
}
#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
{
return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
}
#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
{
return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
}
#define REG_DSI_CMD_DMA_CTRL 0x00000038
#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
#define REG_DSI_CMD_CFG0 0x0000003c
#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
{
return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
}
#define DSI_CMD_CFG0_R_SEL 0x00000010
#define DSI_CMD_CFG0_G_SEL 0x00000100
#define DSI_CMD_CFG0_B_SEL 0x00001000
#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
{
return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
}
#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
}
#define REG_DSI_CMD_CFG1 0x00000040
#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
{
return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
}
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
{
return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
}
#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
#define REG_DSI_DMA_BASE 0x00000044
#define REG_DSI_DMA_LEN 0x00000048
#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
}
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
}
#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
}
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
}
#define REG_DSI_ACK_ERR_STATUS 0x00000064
static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
#define REG_DSI_TRIG_CTRL 0x00000080
#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
{
return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
}
#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
{
return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
}
#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
#define DSI_TRIG_CTRL_STREAM__SHIFT 8
static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
{
return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
}
#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
#define DSI_TRIG_CTRL_TE 0x80000000
#define REG_DSI_TRIG_DMA 0x0000008c
#define REG_DSI_DLN0_PHY_ERR 0x000000b0
#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
#define REG_DSI_LP_TIMER_CTRL 0x000000b4
#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
{
return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
}
#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
{
return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
}
#define REG_DSI_HS_TIMER_CTRL 0x000000b8
#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
{
return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
}
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
{
return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
}
#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
#define REG_DSI_TIMEOUT_STATUS 0x000000bc
#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
{
return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
}
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
{
return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
}
#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
#define REG_DSI_LANE_STATUS 0x000000a4
#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
#define REG_DSI_LANE_CTRL 0x000000a8
#define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
{
return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
}
#define REG_DSI_ERR_INT_MASK0 0x00000108
#define REG_DSI_INTR_CTRL 0x0000010c
#define REG_DSI_RESET 0x00000114
#define REG_DSI_CLK_CTRL 0x00000118
#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
#define DSI_CLK_CTRL_PCLK_ON 0x00000004
#define DSI_CLK_CTRL_DSICLK_ON 0x00000008
#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
#define REG_DSI_CLK_STATUS 0x0000011c
#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
#define REG_DSI_PHY_RESET 0x00000128
#define DSI_PHY_RESET_RESET 0x00000001
#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160
#define REG_DSI_TPG_MAIN_CONTROL 0x00000198
#define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100
#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0
#define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003
#define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0
static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val)
{
return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK;
}
#define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004
#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT 16
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val)
{
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK;
}
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT 8
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val)
{
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK;
}
#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030
#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT 4
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val)
{
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK;
}
#define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002
#define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001
#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168
#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180
#define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001
#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000
#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
{
return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
}
#define DSI_RDBK_DATA_CTRL_CLR 0x00000001
#define REG_DSI_VERSION 0x000001f0
#define DSI_VERSION_MAJOR__MASK 0xff000000
#define DSI_VERSION_MAJOR__SHIFT 24
static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
{
return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
}
#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val)
{
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK;
}
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val)
{
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK;
}
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val)
{
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK;
}
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val)
{
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK;
}
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001
#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001
#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK;
}
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val)
{
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
}
#endif /* DSI_XML */

20
drivers/gpu/drm/msm/dsi/dsi_host.c
View File

@ -55,7 +55,7 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
* scratch register which we never touch)
*/
ver = msm_readl(base + REG_DSI_VERSION);
ver = readl(base + REG_DSI_VERSION);
if (ver) {
/* older dsi host, there is no register shift */
ver = FIELD(ver, DSI_VERSION_MAJOR);
@ -73,12 +73,12 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
* registers are shifted down, read DSI_VERSION again with
* the shifted offset
*/
ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
ver = FIELD(ver, DSI_VERSION_MAJOR);
if (ver == MSM_DSI_VER_MAJOR_6G) {
/* 6G version */
*major = ver;
*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
*minor = readl(base + REG_DSI_6G_HW_VERSION);
return 0;
} else {
return -EINVAL;
@ -186,11 +186,11 @@ struct msm_dsi_host {
static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
{
return msm_readl(msm_host->ctrl_base + reg);
return readl(msm_host->ctrl_base + reg);
}
static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
{
msm_writel(data, msm_host->ctrl_base + reg);
writel(data, msm_host->ctrl_base + reg);
}
static const struct msm_dsi_cfg_handler *dsi_get_config(
@ -356,8 +356,8 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
{
int ret;
DBG("Set clk rates: pclk=%d, byteclk=%lu",
msm_host->mode->clock, msm_host->byte_clk_rate);
DBG("Set clk rates: pclk=%lu, byteclk=%lu",
msm_host->pixel_clk_rate, msm_host->byte_clk_rate);
ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
msm_host->byte_clk_rate);
@ -430,9 +430,9 @@ int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
{
int ret;
DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
msm_host->mode->clock, msm_host->byte_clk_rate,
msm_host->esc_clk_rate, msm_host->src_clk_rate);
DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
msm_host->pixel_clk_rate, msm_host->byte_clk_rate,
msm_host->esc_clk_rate, msm_host->src_clk_rate);
ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
if (ret) {

79
drivers/gpu/drm/msm/dsi/dsi_manager.c
View File

@ -423,7 +423,18 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
return msm_dsi_host_check_dsc(host, mode);
}
static int dsi_mgr_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
int id = dsi_mgr_bridge_get_id(bridge);
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
return drm_bridge_attach(bridge->encoder, msm_dsi->next_bridge,
bridge, flags);
}
static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
.attach = dsi_mgr_bridge_attach,
.pre_enable = dsi_mgr_bridge_pre_enable,
.post_disable = dsi_mgr_bridge_post_disable,
.mode_set = dsi_mgr_bridge_mode_set,
@ -431,17 +442,19 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
};
/* initialize bridge */
struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
struct drm_encoder *encoder)
int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi,
struct drm_encoder *encoder)
{
struct drm_device *dev = msm_dsi->dev;
struct drm_bridge *bridge;
struct dsi_bridge *dsi_bridge;
struct drm_connector *connector;
int ret;
dsi_bridge = devm_kzalloc(msm_dsi->dev->dev,
sizeof(*dsi_bridge), GFP_KERNEL);
if (!dsi_bridge)
return ERR_PTR(-ENOMEM);
return -ENOMEM;
dsi_bridge->id = msm_dsi->id;
@ -450,60 +463,22 @@ struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
ret = devm_drm_bridge_add(msm_dsi->dev->dev, bridge);
if (ret)
return ERR_PTR(ret);
return ret;
ret = drm_bridge_attach(encoder, bridge, NULL, 0);
ret = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret)
return ERR_PTR(ret);
return ret;
return bridge;
}
int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge)
{
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct drm_device *dev = msm_dsi->dev;
struct drm_encoder *encoder;
struct drm_bridge *ext_bridge;
int ret;
ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev,
msm_dsi->pdev->dev.of_node, 1, 0);
if (IS_ERR(ext_bridge))
return PTR_ERR(ext_bridge);
encoder = int_bridge->encoder;
/*
* Try first to create the bridge without it creating its own
* connector.. currently some bridges support this, and others
* do not (and some support both modes)
*/
ret = drm_bridge_attach(encoder, ext_bridge, int_bridge,
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret == -EINVAL) {
/*
* link the internal dsi bridge to the external bridge,
* connector is created by the next bridge.
*/
ret = drm_bridge_attach(encoder, ext_bridge, int_bridge, 0);
if (ret < 0)
return ret;
} else {
struct drm_connector *connector;
/* We are in charge of the connector, create one now. */
connector = drm_bridge_connector_init(dev, encoder);
if (IS_ERR(connector)) {
DRM_ERROR("Unable to create bridge connector\n");
return PTR_ERR(connector);
}
ret = drm_connector_attach_encoder(connector, encoder);
if (ret < 0)
return ret;
connector = drm_bridge_connector_init(dev, encoder);
if (IS_ERR(connector)) {
DRM_ERROR("Unable to create bridge connector\n");
return PTR_ERR(connector);
}
ret = drm_connector_attach_encoder(connector, encoder);
if (ret < 0)
return ret;
return 0;
}

227
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
View File

@ -1,227 +0,0 @@
#ifndef DSI_PHY_10NM_XML
#define DSI_PHY_10NM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
#endif /* DSI_PHY_10NM_XML */

309
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
View File

@ -1,309 +0,0 @@
#ifndef DSI_PHY_14NM_XML
#define DSI_PHY_14NM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
{
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
}
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
{
return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
}
#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
{
return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
}
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
#endif /* DSI_PHY_14NM_XML */

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drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
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@ -1,237 +0,0 @@
#ifndef DSI_PHY_20NM_XML
#define DSI_PHY_20NM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
}
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
#endif /* DSI_PHY_20NM_XML */

384
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
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@ -1,384 +0,0 @@
#ifndef DSI_PHY_28NM_XML
#define DSI_PHY_28NM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
}
#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}
#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
{
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
#endif /* DSI_PHY_28NM_XML */

286
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
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@ -1,286 +0,0 @@
#ifndef DSI_PHY_28NM_8960_XML
#define DSI_PHY_28NM_8960_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
}
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}
#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
#endif /* DSI_PHY_28NM_8960_XML */

483
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
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@ -1,483 +0,0 @@
#ifndef DSI_PHY_7NM_XML
#define DSI_PHY_7NM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 0x000001ac
static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
#endif /* DSI_PHY_7NM_XML */

131
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
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@ -1,131 +0,0 @@
#ifndef MMSS_CC_XML
#define MMSS_CC_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum mmss_cc_clk {
CLK = 0,
PCLK = 1,
};
#define REG_MMSS_CC_AHB 0x00000008
static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
{
switch (idx) {
case CLK: return 0x0000004c;
case PCLK: return 0x00000130;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
#define MMSS_CC_CLK_CC_CLK_EN 0x00000001
#define MMSS_CC_CLK_CC_ROOT_EN 0x00000004
#define MMSS_CC_CLK_CC_MND_EN 0x00000020
#define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0
#define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6
static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
{
return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
}
#define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300
#define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8
static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
{
return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
}
static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
#define MMSS_CC_CLK_MD_D__MASK 0x000000ff
#define MMSS_CC_CLK_MD_D__SHIFT 0
static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
{
return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
}
#define MMSS_CC_CLK_MD_M__MASK 0x0000ff00
#define MMSS_CC_CLK_MD_M__SHIFT 8
static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
{
return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
}
static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
#define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f
#define MMSS_CC_CLK_NS_SRC__SHIFT 0
static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
{
return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
}
#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000
#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12
static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
{
return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
}
#define MMSS_CC_CLK_NS_VAL__MASK 0xff000000
#define MMSS_CC_CLK_NS_VAL__SHIFT 24
static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
{
return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
}
#define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094
#define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4
#define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264
#endif /* MMSS_CC_XML */

8
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
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@ -12,10 +12,10 @@
#include "dsi.h"
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
#define dsi_phy_read(offset) readl((offset))
#define dsi_phy_write(offset, data) writel((data), (offset))
#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);

70
drivers/gpu/drm/msm/dsi/sfpb.xml.h
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@ -1,70 +0,0 @@
#ifndef SFPB_XML
#define SFPB_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum sfpb_ahb_arb_master_port_en {
SFPB_MASTER_PORT_ENABLE = 3,
SFPB_MASTER_PORT_DISABLE = 0,
};
#define REG_SFPB_GPREG 0x00000058
#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800
#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11
static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val)
{
return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK;
}
#endif /* SFPB_XML */

2
drivers/gpu/drm/msm/hdmi/hdmi.c
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@ -5,8 +5,8 @@
* Author: Rob Clark <robdclark@gmail.com>
*/
#include <linux/gpio/consumer.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>

10
drivers/gpu/drm/msm/hdmi/hdmi.h
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@ -115,17 +115,17 @@ void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
{
msm_writel(data, hdmi->mmio + reg);
writel(data, hdmi->mmio + reg);
}
static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
{
return msm_readl(hdmi->mmio + reg);
return readl(hdmi->mmio + reg);
}
static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
{
return msm_readl(hdmi->qfprom_mmio + reg);
return readl(hdmi->qfprom_mmio + reg);
}
/*
@ -166,12 +166,12 @@ struct hdmi_phy {
static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
{
msm_writel(data, phy->mmio + reg);
writel(data, phy->mmio + reg);
}
static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
{
return msm_readl(phy->mmio + reg);
return readl(phy->mmio + reg);
}
int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);

1399
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
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