dt-bindings: riscv: convert plic bindings to json-schema
Convert device tree bindings for SiFive's PLIC to YAML format Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> Link: https://lore.kernel.org/r/1601393531-2402-3-git-send-email-sagar.kadam@sifive.com Signed-off-by: Rob Herring <robh@kernel.org>
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Sagar Kadam
Rob Herring
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406171bf9a
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c825a081c1
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SiFive Platform-Level Interrupt Controller (PLIC)
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-------------------------------------------------
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SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
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(PLIC) high-level specification in the RISC-V Privileged Architecture
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specification. The PLIC connects all external interrupts in the system to all
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hart contexts in the system, via the external interrupt source in each hart.
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A hart context is a privilege mode in a hardware execution thread. For example,
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in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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privilege modes per hart; machine mode and supervisor mode.
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Each interrupt can be enabled on per-context basis. Any context can claim
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a pending enabled interrupt and then release it once it has been handled.
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Each interrupt has a configurable priority. Higher priority interrupts are
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serviced first. Each context can specify a priority threshold. Interrupts
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with priority below this threshold will not cause the PLIC to raise its
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interrupt line leading to the context.
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While the PLIC supports both edge-triggered and level-triggered interrupts,
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interrupt handlers are oblivious to this distinction and therefore it is not
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specified in the PLIC device-tree binding.
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While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
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contains a specific memory layout, which is documented in chapter 8 of the
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SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
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Required properties:
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- compatible : "sifive,plic-1.0.0" and a string identifying the actual
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detailed implementation in case that specific bugs need to be worked around.
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- #address-cells : should be <0> or more.
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- #interrupt-cells : should be <1> or more.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- reg : Should contain 1 register range (address and length).
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- interrupts-extended : Specifies which contexts are connected to the PLIC,
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with "-1" specifying that a context is not present. Each node pointed
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to should be a riscv,cpu-intc node, which has a riscv node as parent.
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- riscv,ndev: Specifies how many external interrupts are supported by
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this controller.
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Example:
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plic: interrupt-controller@c000000 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
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interrupt-controller;
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interrupts-extended = <
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&cpu0-intc 11
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&cpu1-intc 11 &cpu1-intc 9
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&cpu2-intc 11 &cpu2-intc 9
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&cpu3-intc 11 &cpu3-intc 9
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&cpu4-intc 11 &cpu4-intc 9>;
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reg = <0xc000000 0x4000000>;
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riscv,ndev = <10>;
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};
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@ -0,0 +1,97 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive Platform-Level Interrupt Controller (PLIC)
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description:
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SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
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(PLIC) high-level specification in the RISC-V Privileged Architecture
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specification. The PLIC connects all external interrupts in the system to all
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hart contexts in the system, via the external interrupt source in each hart.
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A hart context is a privilege mode in a hardware execution thread. For example,
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in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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privilege modes per hart; machine mode and supervisor mode.
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Each interrupt can be enabled on per-context basis. Any context can claim
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a pending enabled interrupt and then release it once it has been handled.
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Each interrupt has a configurable priority. Higher priority interrupts are
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serviced first. Each context can specify a priority threshold. Interrupts
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with priority below this threshold will not cause the PLIC to raise its
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interrupt line leading to the context.
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While the PLIC supports both edge-triggered and level-triggered interrupts,
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interrupt handlers are oblivious to this distinction and therefore it is not
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specified in the PLIC device-tree binding.
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While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
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contains a specific memory layout, which is documented in chapter 8 of the
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SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
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maintainers:
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- Sagar Kadam <sagar.kadam@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@dabbelt.com>
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-plic
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- const: sifive,plic-1.0.0
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reg:
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maxItems: 1
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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interrupts-extended:
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minItems: 1
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description:
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Specifies which contexts are connected to the PLIC, with "-1" specifying
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that a context is not present. Each node pointed to should be a
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riscv,cpu-intc node, which has a riscv node as parent.
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riscv,ndev:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description:
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Specifies how many external interrupts are supported by this controller.
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required:
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- compatible
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- '#address-cells'
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- '#interrupt-cells'
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- interrupt-controller
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- reg
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- interrupts-extended
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- riscv,ndev
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additionalProperties: false
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examples:
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- |
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plic: interrupt-controller@c000000 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 11
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&cpu1_intc 11 &cpu1_intc 9
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&cpu2_intc 11 &cpu2_intc 9
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&cpu3_intc 11 &cpu3_intc 9
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&cpu4_intc 11 &cpu4_intc 9>;
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reg = <0xc000000 0x4000000>;
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riscv,ndev = <10>;
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};
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