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arm64: dts: qcom: sc7180: Add Last level cache controller node

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Add device tree node for LLCC aka system cache controller for
SC7180 SoC.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ef3394291-2290a8be-91c9-4d46-b5ca-acd5277eb6e2-000000@us-west-2.amazonses.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sai Prakash Ranjan 2019-12-11 04:30:46 +00:00 committed by Bjorn Andersson
parent fb2d815006
commit c831fa2999
1 changed files with 7 additions and 0 deletions
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7
arch/arm64/boot/dts/qcom/sc7180.dtsi
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@ -911,6 +911,13 @@ qspi: spi@88dc000 {
status = "disabled";
};
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,