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drm/i915: Move SST DP link retraining into the ->post_hotplug() hook
Doing link retraining from the short pulse handler is problematic since that might introduce deadlocks with MST sideband processing. Currently we don't retrain MST links from this code, but we want to change that. So better to move the entire thing to the hotplug work. We can utilize the new encoder->hotplug() hook for this. The only thing we leave in the short pulse handler is the link status check. That one still depends on the link parameters stored under intel_dp, so no locking around that but races should be mostly harmless as the actual retraining code will recheck the link state if we end up there by mistake. v2: Rebase due to ->post_hotplug() now being just ->hotplug() Check the connector type to figure out if we should do the HDMI thing or the DP think for DDI [pushed with whitespace changes for sparse] Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180117192149.17760-3-ville.syrjala@linux.intel.com
This commit is contained in:
parent
dba14b27dd
commit
c85d200e83
3 changed files with 123 additions and 90 deletions
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@ -2923,7 +2923,10 @@ static bool intel_ddi_hotplug(struct intel_encoder *encoder,
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drm_modeset_acquire_init(&ctx, 0);
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for (;;) {
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ret = intel_hdmi_reset_link(encoder, &ctx);
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if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
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ret = intel_hdmi_reset_link(encoder, &ctx);
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else
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ret = intel_dp_retrain_link(encoder, &ctx);
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if (ret == -EDEADLK) {
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drm_modeset_backoff(&ctx);
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@ -3056,10 +3059,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
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drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
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DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
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if (init_hdmi)
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intel_encoder->hotplug = intel_ddi_hotplug;
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else
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intel_encoder->hotplug = intel_encoder_hotplug;
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intel_encoder->hotplug = intel_ddi_hotplug;
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intel_encoder->compute_output_type = intel_ddi_compute_output_type;
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intel_encoder->compute_config = intel_ddi_compute_config;
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intel_encoder->enable = intel_enable_ddi;
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@ -4272,12 +4272,84 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
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return -EINVAL;
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}
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static void
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intel_dp_retrain_link(struct intel_dp *intel_dp)
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static bool
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intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
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{
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u8 link_status[DP_LINK_STATUS_SIZE];
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if (!intel_dp_get_link_status(intel_dp, link_status)) {
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DRM_ERROR("Failed to get link status\n");
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return false;
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}
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/*
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* Validate the cached values of intel_dp->link_rate and
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* intel_dp->lane_count before attempting to retrain.
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*/
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if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
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intel_dp->lane_count))
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return false;
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/* Retrain if Channel EQ or CR not ok */
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return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
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}
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/*
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* If display is now connected check links status,
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* there has been known issues of link loss triggering
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* long pulse.
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*
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* Some sinks (eg. ASUS PB287Q) seem to perform some
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* weird HPD ping pong during modesets. So we can apparently
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* end up with HPD going low during a modeset, and then
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* going back up soon after. And once that happens we must
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* retrain the link to get a picture. That's in case no
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* userspace component reacted to intermittent HPD dip.
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*/
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int intel_dp_retrain_link(struct intel_encoder *encoder,
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struct drm_modeset_acquire_ctx *ctx)
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{
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_connector *connector = intel_dp->attached_connector;
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struct drm_connector_state *conn_state;
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struct intel_crtc_state *crtc_state;
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struct intel_crtc *crtc;
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int ret;
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/* FIXME handle the MST connectors as well */
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if (!connector || connector->base.status != connector_status_connected)
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return 0;
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ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
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ctx);
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if (ret)
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return ret;
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conn_state = connector->base.state;
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crtc = to_intel_crtc(conn_state->crtc);
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if (!crtc)
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return 0;
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ret = drm_modeset_lock(&crtc->base.mutex, ctx);
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if (ret)
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return ret;
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crtc_state = to_intel_crtc_state(crtc->base.state);
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WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
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if (!crtc_state->base.active)
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return 0;
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if (conn_state->commit &&
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!try_wait_for_completion(&conn_state->commit->hw_done))
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return 0;
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if (!intel_dp_needs_link_retrain(intel_dp))
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return 0;
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/* Suppress underruns caused by re-training */
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
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@ -4295,51 +4367,49 @@ intel_dp_retrain_link(struct intel_dp *intel_dp)
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if (crtc->config->has_pch_encoder)
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intel_set_pch_fifo_underrun_reporting(dev_priv,
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intel_crtc_pch_transcoder(crtc), true);
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return 0;
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}
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static void
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intel_dp_check_link_status(struct intel_dp *intel_dp)
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/*
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* If display is now connected check links status,
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* there has been known issues of link loss triggering
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* long pulse.
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*
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* Some sinks (eg. ASUS PB287Q) seem to perform some
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* weird HPD ping pong during modesets. So we can apparently
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* end up with HPD going low during a modeset, and then
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* going back up soon after. And once that happens we must
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* retrain the link to get a picture. That's in case no
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* userspace component reacted to intermittent HPD dip.
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*/
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static bool intel_dp_hotplug(struct intel_encoder *encoder,
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struct intel_connector *connector)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
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struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
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struct drm_connector_state *conn_state =
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intel_dp->attached_connector->base.state;
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u8 link_status[DP_LINK_STATUS_SIZE];
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struct drm_modeset_acquire_ctx ctx;
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bool changed;
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int ret;
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WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
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changed = intel_encoder_hotplug(encoder, connector);
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if (!intel_dp_get_link_status(intel_dp, link_status)) {
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DRM_ERROR("Failed to get link status\n");
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return;
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drm_modeset_acquire_init(&ctx, 0);
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for (;;) {
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ret = intel_dp_retrain_link(encoder, &ctx);
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if (ret == -EDEADLK) {
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drm_modeset_backoff(&ctx);
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continue;
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}
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break;
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}
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if (!conn_state->crtc)
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return;
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drm_modeset_drop_locks(&ctx);
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drm_modeset_acquire_fini(&ctx);
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WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
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WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex));
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if (!conn_state->crtc->state->active)
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return;
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if (conn_state->commit &&
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!try_wait_for_completion(&conn_state->commit->hw_done))
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return;
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/*
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* Validate the cached values of intel_dp->link_rate and
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* intel_dp->lane_count before attempting to retrain.
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*/
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if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
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intel_dp->lane_count))
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return;
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/* Retrain if Channel EQ or CR not ok */
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if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
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DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
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intel_encoder->base.name);
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intel_dp_retrain_link(intel_dp);
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}
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return changed;
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}
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/*
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@ -4397,7 +4467,9 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
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DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
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}
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intel_dp_check_link_status(intel_dp);
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/* defer to the hotplug work for link retraining if needed */
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if (intel_dp_needs_link_retrain(intel_dp))
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return false;
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if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
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DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
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@ -4782,20 +4854,6 @@ intel_dp_long_pulse(struct intel_connector *connector)
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*/
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status = connector_status_disconnected;
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goto out;
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} else {
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/*
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* If display is now connected check links status,
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* there has been known issues of link loss triggerring
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* long pulse.
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*
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* Some sinks (eg. ASUS PB287Q) seem to perform some
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* weird HPD ping pong during modesets. So we can apparently
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* end up with HPD going low during a modeset, and then
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* going back up soon after. And once that happens we must
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* retrain the link to get a picture. That's in case no
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* userspace component reacted to intermittent HPD dip.
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*/
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intel_dp_check_link_status(intel_dp);
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}
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/*
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@ -5372,37 +5430,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
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}
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if (!intel_dp->is_mst) {
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struct drm_modeset_acquire_ctx ctx;
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struct drm_connector *connector = &intel_dp->attached_connector->base;
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struct drm_crtc *crtc;
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int iret;
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bool handled = false;
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drm_modeset_acquire_init(&ctx, 0);
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retry:
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iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
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if (iret)
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goto err;
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crtc = connector->state->crtc;
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if (crtc) {
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iret = drm_modeset_lock(&crtc->mutex, &ctx);
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if (iret)
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goto err;
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}
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bool handled;
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handled = intel_dp_short_pulse(intel_dp);
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err:
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if (iret == -EDEADLK) {
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drm_modeset_backoff(&ctx);
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goto retry;
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}
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drm_modeset_drop_locks(&ctx);
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drm_modeset_acquire_fini(&ctx);
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WARN(iret, "Acquiring modeset locks failed with %i\n", iret);
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/* Short pulse can signify loss of hdcp authentication */
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intel_hdcp_check_link(intel_dp->attached_connector);
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@ -6393,7 +6424,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
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"DP %c", port_name(port)))
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goto err_encoder_init;
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intel_encoder->hotplug = intel_encoder_hotplug;
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intel_encoder->hotplug = intel_dp_hotplug;
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intel_encoder->compute_config = intel_dp_compute_config;
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intel_encoder->get_hw_state = intel_dp_get_hw_state;
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intel_encoder->get_config = intel_dp_get_config;
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@ -1626,6 +1626,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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int link_rate, uint8_t lane_count);
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp);
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int intel_dp_retrain_link(struct intel_encoder *encoder,
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struct drm_modeset_acquire_ctx *ctx);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_encoder_reset(struct drm_encoder *encoder);
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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