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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 02:50:43 +00:00
spi: sirf: refactor spi transfer functions
split sirfsoc_spi_transfer function into 3 sub-functions: spi_sirfsoc_cmd_transfer, spi_sirfsoc_pio_transfer and spi_sirfsoc_dma_transfer. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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parent
bf83fd6402
commit
c908ef345d
1 changed files with 123 additions and 109 deletions
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@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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@ -309,59 +310,51 @@ static void spi_sirfsoc_dma_fini_callback(void *data)
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complete(dma_complete);
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}
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static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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static int spi_sirfsoc_cmd_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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int timeout = t->len * 10;
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u32 cmd;
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sspi = spi_master_get_devdata(spi->master);
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sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
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sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
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sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
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reinit_completion(&sspi->rx_done);
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reinit_completion(&sspi->tx_done);
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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/*
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* fill tx_buf into command register and wait for its completion
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*/
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if (sspi->tx_by_cmd) {
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u32 cmd;
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memcpy(&cmd, sspi->tx, t->len);
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if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
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cmd = cpu_to_be32(cmd) >>
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((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
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if (sspi->word_width == 2 && t->len == 4 &&
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(!(spi->mode & SPI_LSB_FIRST)))
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cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
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writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
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writel(SIRFSOC_SPI_FRM_END_INT_EN,
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sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_CMD_TX_EN,
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sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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return 0;
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}
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return t->len;
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memcpy(&cmd, sspi->tx, t->len);
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if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
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cmd = cpu_to_be32(cmd) >>
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((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
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if (sspi->word_width == 2 && t->len == 4 &&
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(!(spi->mode & SPI_LSB_FIRST)))
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cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
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writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
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writel(SIRFSOC_SPI_FRM_END_INT_EN,
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sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_CMD_TX_EN,
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sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "cmd transfer timeout\n");
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return 0;
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}
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if (sspi->left_tx_word == 1) {
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return t->len;
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}
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static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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struct dma_async_tx_descriptor *rx_desc, *tx_desc;
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int timeout = t->len * 10;
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sspi = spi_master_get_devdata(spi->master);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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} else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
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SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_MUL_DAT_MODE |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(sspi->left_tx_word - 1,
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sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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@ -373,88 +366,109 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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}
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sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
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(t->tx_buf != t->rx_buf) ?
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DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
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rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
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sspi->dst_start, t->len, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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rx_desc->callback = spi_sirfsoc_dma_fini_callback;
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rx_desc->callback_param = &sspi->rx_done;
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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if (IS_DMA_VALID(t)) {
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struct dma_async_tx_descriptor *rx_desc, *tx_desc;
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sspi->dst_start = dma_map_single(&spi->dev,
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sspi->rx, t->len, (t->tx_buf != t->rx_buf) ?
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DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
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rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
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sspi->dst_start, t->len, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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rx_desc->callback = spi_sirfsoc_dma_fini_callback;
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rx_desc->callback_param = &sspi->rx_done;
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sspi->src_start = dma_map_single(&spi->dev,
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(void *)sspi->tx, t->len,
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(t->tx_buf != t->rx_buf) ?
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DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
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tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
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sspi->src_start, t->len, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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tx_desc->callback = spi_sirfsoc_dma_fini_callback;
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tx_desc->callback_param = &sspi->tx_done;
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dmaengine_submit(tx_desc);
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dmaengine_submit(rx_desc);
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dma_async_issue_pending(sspi->tx_chan);
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dma_async_issue_pending(sspi->rx_chan);
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} else {
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/* Send the first word to trigger the whole tx/rx process */
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sspi->tx_word(sspi);
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writel(SIRFSOC_SPI_RX_OFLOW_INT_EN |
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SIRFSOC_SPI_TX_UFLOW_INT_EN |
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SIRFSOC_SPI_RXFIFO_THD_INT_EN |
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SIRFSOC_SPI_TXFIFO_THD_INT_EN |
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SIRFSOC_SPI_FRM_END_INT_EN |
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SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
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SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN,
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sspi->base + SIRFSOC_SPI_INT_EN);
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}
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sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
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(t->tx_buf != t->rx_buf) ?
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DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
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tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
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sspi->src_start, t->len, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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tx_desc->callback = spi_sirfsoc_dma_fini_callback;
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tx_desc->callback_param = &sspi->tx_done;
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dmaengine_submit(tx_desc);
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dmaengine_submit(rx_desc);
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dma_async_issue_pending(sspi->tx_chan);
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dma_async_issue_pending(sspi->rx_chan);
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writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
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sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (!IS_DMA_VALID(t)) { /* for PIO */
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if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
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dev_err(&spi->dev, "transfer timeout\n");
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} else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
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if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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dmaengine_terminate_all(sspi->rx_chan);
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} else
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sspi->left_rx_word = 0;
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/*
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* we only wait tx-done event if transferring by DMA. for PIO,
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* we get rx data by writing tx data, so if rx is done, tx has
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* done earlier
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*/
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if (IS_DMA_VALID(t)) {
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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dmaengine_terminate_all(sspi->tx_chan);
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}
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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dmaengine_terminate_all(sspi->tx_chan);
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}
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if (IS_DMA_VALID(t)) {
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dma_unmap_single(&spi->dev,
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sspi->src_start, t->len, DMA_TO_DEVICE);
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dma_unmap_single(&spi->dev,
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sspi->dst_start, t->len, DMA_FROM_DEVICE);
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}
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dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
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dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
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/* TX, RX FIFO stop */
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writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX)
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writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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}
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static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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int timeout = t->len * 10;
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sspi = spi_master_get_devdata(spi->master);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | SIRFSOC_SPI_MUL_DAT_MODE |
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SIRFSOC_SPI_ENA_AUTO_CLR, sspi->base + SIRFSOC_SPI_CTRL);
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writel(sspi->left_tx_word - 1,
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sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(sspi->left_rx_word - 1,
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sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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sspi->tx_word(sspi);
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writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
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SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_RXFIFO_THD_INT_EN |
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SIRFSOC_SPI_TXFIFO_THD_INT_EN | SIRFSOC_SPI_FRM_END_INT_EN|
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SIRFSOC_SPI_RXFIFO_FULL_INT_EN,
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sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
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sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
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dev_err(&spi->dev, "transfer timeout\n");
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writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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sspi = spi_master_get_devdata(spi->master);
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sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
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sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
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sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
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reinit_completion(&sspi->rx_done);
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reinit_completion(&sspi->tx_done);
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/*
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* in the transfer, if transfer data using command register with rx_buf
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* null, just fill command data into command register and wait for its
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* completion.
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*/
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if (sspi->tx_by_cmd)
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spi_sirfsoc_cmd_transfer(spi, t);
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else if (IS_DMA_VALID(t))
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spi_sirfsoc_dma_transfer(spi, t);
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else
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spi_sirfsoc_pio_transfer(spi, t);
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return t->len - sspi->left_rx_word * sspi->word_width;
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}
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