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drm/i915: Add some L3 registers to the parser whitelist

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Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Brad Volkin 2014-06-17 14:10:34 -07:00 committed by Daniel Vetter
parent beff0d0f61
commit c9224faa59
2 changed files with 5 additions and 0 deletions
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3
drivers/gpu/drm/i915/i915_cmd_parser.c
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@ -426,6 +426,9 @@ static const u32 gen7_render_regs[] = {
GEN7_SO_WRITE_OFFSET(1),
GEN7_SO_WRITE_OFFSET(2),
GEN7_SO_WRITE_OFFSET(3),
GEN7_L3SQCREG1,
GEN7_L3CNTLREG2,
GEN7_L3CNTLREG3,
};
static const u32 gen7_blt_regs[] = {

2
drivers/gpu/drm/i915/i915_reg.h
View file

@ -4670,6 +4670,8 @@ enum punit_power_well {
#define GEN7_L3CNTLREG1 0xB01C
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
#define GEN7_L3AGDIS (1<<19)
#define GEN7_L3CNTLREG2 0xB020
#define GEN7_L3CNTLREG3 0xB024
#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000