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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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mmc: sdhci-msm: add Inline Crypto Engine support
Add support for Qualcomm Inline Crypto Engine (ICE) to sdhci-msm.
The standard-compliant parts, such as querying the crypto capabilities
and enabling crypto for individual MMC requests, are already handled by
cqhci-crypto.c, which itself is wired into the blk-crypto framework.
However, ICE requires vendor-specific init, enable, and resume logic,
and it requires that keys be programmed and evicted by vendor-specific
SMC calls. Make the sdhci-msm driver handle these details.
This is heavily inspired by the similar changes made for UFS, since the
UFS and eMMC ICE instances are very similar. See commit df4ec2fa7a
("scsi: ufs-qcom: Add Inline Crypto Engine support").
I tested this on a Sony Xperia 10, which uses the Snapdragon 630 SoC,
which has basic upstream support. Mainly, I used android-xfstests
(https://github.com/tytso/xfstests-bld/blob/master/Documentation/android-xfstests.md)
to run the ext4 and f2fs encryption tests in a Debian chroot:
android-xfstests -c ext4,f2fs -g encrypt -m inlinecrypt
These tests included tests which verify that the on-disk ciphertext is
identical to that produced by a software implementation. I also
verified that ICE was actually being used.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Satya Tangirala <satyat@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20210126001456.382989-9-ebiggers@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Eric Biggers
Ulf Hansson
parent
5cc046eb13
commit
c93767cf64
2 changed files with 273 additions and 4 deletions
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@ -546,6 +546,7 @@ config MMC_SDHCI_MSM
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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select MMC_CQHCI
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select QCOM_SCM if MMC_CRYPTO && ARCH_QCOM
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in Qualcomm SOCs. The controller supports
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@ -13,6 +13,7 @@
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#include <linux/iopoll.h>
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#include <linux/qcom_scm.h>
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#include <linux/regulator/consumer.h>
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#include <linux/interconnect.h>
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#include <linux/pinctrl/consumer.h>
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@ -255,10 +256,12 @@ struct sdhci_msm_variant_info {
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struct sdhci_msm_host {
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struct platform_device *pdev;
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void __iomem *core_mem; /* MSM SDCC mapped address */
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void __iomem *ice_mem; /* MSM ICE mapped address (if available) */
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int pwr_irq; /* power irq */
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struct clk *bus_clk; /* SDHC bus voter clock */
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struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
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struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
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/* core, iface, cal, sleep, and ice clocks */
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struct clk_bulk_data bulk_clks[5];
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unsigned long clk_rate;
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struct mmc_host *mmc;
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struct opp_table *opp_table;
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@ -1792,6 +1795,246 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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__sdhci_msm_set_clock(host, clock);
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}
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/*****************************************************************************\
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* *
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* Inline Crypto Engine (ICE) support *
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* *
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\*****************************************************************************/
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#ifdef CONFIG_MMC_CRYPTO
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#define AES_256_XTS_KEY_SIZE 64
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/* QCOM ICE registers */
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#define QCOM_ICE_REG_VERSION 0x0008
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#define QCOM_ICE_REG_FUSE_SETTING 0x0010
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#define QCOM_ICE_FUSE_SETTING_MASK 0x1
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#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
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#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
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#define QCOM_ICE_REG_BIST_STATUS 0x0070
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#define QCOM_ICE_BIST_STATUS_MASK 0xF0000000
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#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000
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#define sdhci_msm_ice_writel(host, val, reg) \
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writel((val), (host)->ice_mem + (reg))
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#define sdhci_msm_ice_readl(host, reg) \
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readl((host)->ice_mem + (reg))
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static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host)
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{
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struct device *dev = mmc_dev(msm_host->mmc);
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u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION);
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int major = regval >> 24;
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int minor = (regval >> 16) & 0xFF;
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int step = regval & 0xFFFF;
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/* For now this driver only supports ICE version 3. */
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if (major != 3) {
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dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
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major, minor, step);
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return false;
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}
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dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
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major, minor, step);
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/* If fuses are blown, ICE might not work in the standard way. */
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regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING);
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if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
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QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
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QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
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dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
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return false;
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}
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return true;
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}
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static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
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{
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return devm_clk_get(dev, "ice");
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}
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static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
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struct cqhci_host *cq_host)
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{
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struct mmc_host *mmc = msm_host->mmc;
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struct device *dev = mmc_dev(mmc);
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struct resource *res;
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int err;
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if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
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return 0;
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res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM,
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"ice");
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if (!res) {
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dev_warn(dev, "ICE registers not found\n");
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goto disable;
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}
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if (!qcom_scm_ice_available()) {
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dev_warn(dev, "ICE SCM interface not found\n");
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goto disable;
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}
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msm_host->ice_mem = devm_ioremap_resource(dev, res);
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if (IS_ERR(msm_host->ice_mem)) {
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err = PTR_ERR(msm_host->ice_mem);
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dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
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return err;
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}
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if (!sdhci_msm_ice_supported(msm_host))
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goto disable;
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mmc->caps2 |= MMC_CAP2_CRYPTO;
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return 0;
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disable:
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dev_warn(dev, "Disabling inline encryption support\n");
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return 0;
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}
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static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host)
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{
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u32 regval;
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regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
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/*
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* Enable low power mode sequence
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* [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
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*/
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regval |= 0x7000;
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sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
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}
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static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host)
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{
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u32 regval;
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/* ICE Optimizations Enable Sequence */
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regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
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regval |= 0xD807100;
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/* ICE HPG requires delay before writing */
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udelay(5);
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sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
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udelay(5);
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}
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/*
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* Wait until the ICE BIST (built-in self-test) has completed.
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*
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* This may be necessary before ICE can be used.
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*
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* Note that we don't really care whether the BIST passed or failed; we really
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* just want to make sure that it isn't still running. This is because (a) the
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* BIST is a FIPS compliance thing that never fails in practice, (b) ICE is
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* documented to reject crypto requests if the BIST fails, so we needn't do it
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* in software too, and (c) properly testing storage encryption requires testing
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* the full storage stack anyway, and not relying on hardware-level self-tests.
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*/
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static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)
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{
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u32 regval;
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int err;
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err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS,
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regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),
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50, 5000);
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if (err)
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dev_err(mmc_dev(msm_host->mmc),
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"Timed out waiting for ICE self-test to complete\n");
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return err;
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}
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static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
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{
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if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
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return;
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sdhci_msm_ice_low_power_mode_enable(msm_host);
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sdhci_msm_ice_optimization_enable(msm_host);
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sdhci_msm_ice_wait_bist_status(msm_host);
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}
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static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
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{
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if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
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return 0;
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return sdhci_msm_ice_wait_bist_status(msm_host);
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}
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/*
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* Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
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* vendor-specific SCM calls for this; it doesn't support the standard way.
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*/
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static int sdhci_msm_program_key(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg,
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int slot)
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{
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struct device *dev = mmc_dev(cq_host->mmc);
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union cqhci_crypto_cap_entry cap;
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union {
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u8 bytes[AES_256_XTS_KEY_SIZE];
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u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
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} key;
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int i;
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int err;
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if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
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return qcom_scm_ice_invalidate_key(slot);
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/* Only AES-256-XTS has been tested so far. */
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cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
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if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
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cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) {
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dev_err_ratelimited(dev,
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"Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
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cap.algorithm_id, cap.key_size);
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return -EINVAL;
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}
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memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
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/*
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* The SCM call byte-swaps the 32-bit words of the key. So we have to
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* do the same, in order for the final key be correct.
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*/
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for (i = 0; i < ARRAY_SIZE(key.words); i++)
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__cpu_to_be32s(&key.words[i]);
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err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
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QCOM_SCM_ICE_CIPHER_AES_256_XTS,
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cfg->data_unit_size);
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memzero_explicit(&key, sizeof(key));
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return err;
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}
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#else /* CONFIG_MMC_CRYPTO */
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static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
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{
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return NULL;
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}
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static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
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struct cqhci_host *cq_host)
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{
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return 0;
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}
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static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
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{
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}
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static inline int __maybe_unused
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sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
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{
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return 0;
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}
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#endif /* !CONFIG_MMC_CRYPTO */
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/*****************************************************************************\
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* *
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* MSM Command Queue Engine (CQE) *
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@ -1810,6 +2053,16 @@ static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
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return 0;
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}
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static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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sdhci_cqe_enable(mmc);
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sdhci_msm_ice_enable(msm_host);
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}
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static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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@ -1842,8 +2095,11 @@ static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
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}
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static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
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.enable = sdhci_cqe_enable,
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.enable = sdhci_msm_cqe_enable,
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.disable = sdhci_msm_cqe_disable,
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#ifdef CONFIG_MMC_CRYPTO
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.program_key = sdhci_msm_program_key,
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#endif
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};
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static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
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@ -1879,6 +2135,10 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
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dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
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ret = sdhci_msm_ice_init(msm_host, cq_host);
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if (ret)
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goto cleanup;
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ret = cqhci_init(cq_host, host->mmc, dma64);
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if (ret) {
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dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
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@ -2319,6 +2579,11 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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clk = NULL;
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msm_host->bulk_clks[3].clk = clk;
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clk = sdhci_msm_ice_get_clk(&pdev->dev);
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if (IS_ERR(clk))
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clk = NULL;
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msm_host->bulk_clks[4].clk = clk;
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
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msm_host->bulk_clks);
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if (ret)
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@ -2532,12 +2797,15 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
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* Whenever core-clock is gated dynamically, it's needed to
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* restore the SDR DLL settings when the clock is ungated.
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*/
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if (msm_host->restore_dll_config && msm_host->clk_rate)
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if (msm_host->restore_dll_config && msm_host->clk_rate) {
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ret = sdhci_msm_restore_sdr_dll_config(host);
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if (ret)
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return ret;
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}
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dev_pm_opp_set_rate(dev, msm_host->clk_rate);
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return ret;
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return sdhci_msm_ice_resume(msm_host);
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}
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static const struct dev_pm_ops sdhci_msm_pm_ops = {
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