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drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
[Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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1 changed files with 3 additions and 3 deletions
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@ -5398,9 +5398,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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v->MaximumReadBandwidthWithPrefetch =
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v->MaximumReadBandwidthWithPrefetch
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+ dml_max4(
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v->VActivePixelBandwidth[i][j][k],
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v->VActiveCursorBandwidth[i][j][k]
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+ dml_max3(
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v->VActivePixelBandwidth[i][j][k]
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+ v->VActiveCursorBandwidth[i][j][k]
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+ v->NoOfDPP[i][j][k]
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* (v->meta_row_bandwidth[i][j][k]
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+ v->dpte_row_bandwidth[i][j][k]),
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