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drm/i915: enable PCH PLL, FDI training and transcoder even for eDP
eDP panels require these to be set up prior to panel power sequencing, or they'll fail to power on due to an "asset not ready" check. And of course, eDP panels attached to anything other than DP_A need them enabled regardless, since they'll be driven from the CPU through FDI out to the PCH. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Jesse Barnes
Chris Wilson
parent
7e7d76c306
commit
c98e9dcf90
1 changed files with 128 additions and 132 deletions
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@ -1889,34 +1889,32 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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}
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}
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if (!HAS_eDP) {
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/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
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temp = I915_READ(fdi_rx_reg);
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/*
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* make the BPC in FDI Rx be consistent with that in
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* pipeconf reg.
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*/
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temp &= ~(0x7 << 16);
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temp |= (pipe_bpc << 11);
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temp &= ~(7 << 19);
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temp |= (intel_crtc->fdi_lanes - 1) << 19;
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I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
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I915_READ(fdi_rx_reg);
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udelay(200);
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/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
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temp = I915_READ(fdi_rx_reg);
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/*
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* make the BPC in FDI Rx be consistent with that in
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* pipeconf reg.
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*/
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temp &= ~(0x7 << 16);
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temp |= (pipe_bpc << 11);
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temp &= ~(7 << 19);
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temp |= (intel_crtc->fdi_lanes - 1) << 19;
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I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
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I915_READ(fdi_rx_reg);
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udelay(200);
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/* Switch from Rawclk to PCDclk */
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temp = I915_READ(fdi_rx_reg);
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I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
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I915_READ(fdi_rx_reg);
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udelay(200);
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/* Switch from Rawclk to PCDclk */
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temp = I915_READ(fdi_rx_reg);
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I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
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I915_READ(fdi_rx_reg);
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udelay(200);
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/* Enable CPU FDI TX PLL, always on for Ironlake */
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temp = I915_READ(fdi_tx_reg);
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if ((temp & FDI_TX_PLL_ENABLE) == 0) {
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I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
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I915_READ(fdi_tx_reg);
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udelay(100);
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}
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/* Enable CPU FDI TX PLL, always on for Ironlake */
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temp = I915_READ(fdi_tx_reg);
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if ((temp & FDI_TX_PLL_ENABLE) == 0) {
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I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
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I915_READ(fdi_tx_reg);
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udelay(100);
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}
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/* Enable panel fitting for LVDS */
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@ -1951,114 +1949,112 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
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}
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if (!HAS_eDP) {
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/* For PCH output, training FDI link */
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if (IS_GEN6(dev))
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gen6_fdi_link_train(crtc);
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else
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ironlake_fdi_link_train(crtc);
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/* For PCH output, training FDI link */
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if (IS_GEN6(dev))
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gen6_fdi_link_train(crtc);
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else
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ironlake_fdi_link_train(crtc);
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/* enable PCH DPLL */
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temp = I915_READ(pch_dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
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I915_READ(pch_dpll_reg);
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}
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udelay(200);
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if (HAS_PCH_CPT(dev)) {
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/* Be sure PCH DPLL SEL is set */
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temp = I915_READ(PCH_DPLL_SEL);
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if (trans_dpll_sel == 0 &&
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(temp & TRANSA_DPLL_ENABLE) == 0)
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temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
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else if (trans_dpll_sel == 1 &&
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(temp & TRANSB_DPLL_ENABLE) == 0)
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temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
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I915_WRITE(PCH_DPLL_SEL, temp);
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I915_READ(PCH_DPLL_SEL);
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}
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/* set transcoder timing */
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I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
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I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
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I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
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I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
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I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
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I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
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/* enable normal train */
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temp = I915_READ(fdi_tx_reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
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FDI_TX_ENHANCE_FRAME_ENABLE);
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I915_READ(fdi_tx_reg);
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temp = I915_READ(fdi_rx_reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_NORMAL_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE;
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}
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I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
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I915_READ(fdi_rx_reg);
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/* wait one idle pattern time */
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udelay(100);
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
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int reg;
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reg = I915_READ(trans_dp_ctl);
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reg &= ~(TRANS_DP_PORT_SEL_MASK |
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TRANS_DP_SYNC_MASK);
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reg |= (TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_ENH_FRAMING);
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if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
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reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
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if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
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reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
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switch (intel_trans_dp_port_sel(crtc)) {
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case PCH_DP_B:
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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case PCH_DP_C:
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reg |= TRANS_DP_PORT_SEL_C;
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break;
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case PCH_DP_D:
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reg |= TRANS_DP_PORT_SEL_D;
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break;
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default:
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DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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}
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I915_WRITE(trans_dp_ctl, reg);
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POSTING_READ(trans_dp_ctl);
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}
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/* enable PCH transcoder */
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temp = I915_READ(transconf_reg);
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/*
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* make the BPC in transcoder be consistent with
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* that in pipeconf reg.
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*/
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temp &= ~PIPE_BPC_MASK;
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temp |= pipe_bpc;
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I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
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I915_READ(transconf_reg);
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if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
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DRM_ERROR("failed to enable transcoder\n");
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/* enable PCH DPLL */
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temp = I915_READ(pch_dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
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I915_READ(pch_dpll_reg);
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}
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udelay(200);
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if (HAS_PCH_CPT(dev)) {
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/* Be sure PCH DPLL SEL is set */
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temp = I915_READ(PCH_DPLL_SEL);
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if (trans_dpll_sel == 0 &&
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(temp & TRANSA_DPLL_ENABLE) == 0)
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temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
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else if (trans_dpll_sel == 1 &&
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(temp & TRANSB_DPLL_ENABLE) == 0)
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temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
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I915_WRITE(PCH_DPLL_SEL, temp);
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I915_READ(PCH_DPLL_SEL);
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}
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/* set transcoder timing */
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I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
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I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
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I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
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I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
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I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
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I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
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/* enable normal train */
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temp = I915_READ(fdi_tx_reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
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FDI_TX_ENHANCE_FRAME_ENABLE);
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I915_READ(fdi_tx_reg);
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temp = I915_READ(fdi_rx_reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_NORMAL_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE;
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}
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I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
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I915_READ(fdi_rx_reg);
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/* wait one idle pattern time */
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udelay(100);
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
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int reg;
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reg = I915_READ(trans_dp_ctl);
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reg &= ~(TRANS_DP_PORT_SEL_MASK |
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TRANS_DP_SYNC_MASK);
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reg |= (TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_ENH_FRAMING);
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if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
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reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
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if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
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reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
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switch (intel_trans_dp_port_sel(crtc)) {
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case PCH_DP_B:
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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case PCH_DP_C:
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reg |= TRANS_DP_PORT_SEL_C;
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break;
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case PCH_DP_D:
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reg |= TRANS_DP_PORT_SEL_D;
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break;
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default:
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DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
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reg |= TRANS_DP_PORT_SEL_B;
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break;
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}
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I915_WRITE(trans_dp_ctl, reg);
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POSTING_READ(trans_dp_ctl);
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}
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/* enable PCH transcoder */
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temp = I915_READ(transconf_reg);
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/*
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* make the BPC in transcoder be consistent with
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* that in pipeconf reg.
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*/
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temp &= ~PIPE_BPC_MASK;
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temp |= pipe_bpc;
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I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
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I915_READ(transconf_reg);
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if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
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DRM_ERROR("failed to enable transcoder\n");
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intel_crtc_load_lut(crtc);
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