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phy: qcom: Utilize UFS reset controller
Move the PHY reset from ufs-qcom into the respective PHYs. This will allow us to merge the two phases of UFS PHY initialization. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
parent
12fd5f250d
commit
c9b589791f
6 changed files with 76 additions and 18 deletions
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@ -897,6 +897,7 @@ struct qmp_phy {
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* @init_count: phy common block initialization count
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* @phy_initialized: indicate if PHY has been initialized
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* @mode: current PHY mode
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* @ufs_reset: optional UFS PHY reset handle
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*/
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struct qcom_qmp {
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struct device *dev;
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@ -914,6 +915,8 @@ struct qcom_qmp {
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int init_count;
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bool phy_initialized;
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enum phy_mode mode;
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struct reset_control *ufs_reset;
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};
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static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
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@ -1314,6 +1317,7 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
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return 0;
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}
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reset_control_assert(qmp->ufs_reset);
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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@ -1351,6 +1355,33 @@ static int qcom_qmp_phy_init(struct phy *phy)
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dev_vdbg(qmp->dev, "Initializing QMP phy\n");
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if (cfg->no_pcs_sw_reset) {
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/*
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* Get UFS reset, which is delayed until now to avoid a
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* circular dependency where UFS needs its PHY, but the PHY
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* needs this UFS reset.
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*/
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if (!qmp->ufs_reset) {
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qmp->ufs_reset =
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devm_reset_control_get_exclusive(qmp->dev,
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"ufsphy");
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if (IS_ERR(qmp->ufs_reset)) {
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ret = PTR_ERR(qmp->ufs_reset);
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dev_err(qmp->dev,
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"failed to get UFS reset: %d\n",
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ret);
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qmp->ufs_reset = NULL;
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return ret;
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}
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}
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ret = reset_control_assert(qmp->ufs_reset);
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if (ret)
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goto err_lane_rst;
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}
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ret = qcom_qmp_phy_com_init(qphy);
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if (ret)
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return ret;
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@ -1383,6 +1414,9 @@ static int qcom_qmp_phy_init(struct phy *phy)
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cfg->rx_tbl, cfg->rx_tbl_num);
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qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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goto err_lane_rst;
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/*
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* UFS PHY requires the deassert of software reset before serdes start.
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@ -19,6 +19,7 @@
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#include <linux/clk.h>
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#include <linux/phy/phy.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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@ -101,6 +102,7 @@ struct ufs_qcom_phy {
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struct ufs_qcom_phy_specific_ops *phy_spec_ops;
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enum phy_mode mode;
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struct reset_control *ufs_reset;
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};
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/**
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@ -132,6 +134,7 @@ struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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struct ufs_qcom_phy *common_cfg,
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const struct phy_ops *ufs_qcom_phy_gen_ops,
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struct ufs_qcom_phy_specific_ops *phy_spec_ops);
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int ufs_qcom_phy_get_reset(struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
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struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
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@ -48,6 +48,14 @@ static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
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bool is_rate_B = false;
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int ret;
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ret = ufs_qcom_phy_get_reset(phy_common);
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if (ret)
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return ret;
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ret = reset_control_assert(phy_common->ufs_reset);
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if (ret)
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return ret;
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if (phy_common->mode == PHY_MODE_UFS_HS_B)
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is_rate_B = true;
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@ -67,6 +67,14 @@ static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
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bool is_rate_B = false;
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int ret;
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ret = ufs_qcom_phy_get_reset(phy_common);
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if (ret)
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return ret;
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ret = reset_control_assert(phy_common->ufs_reset);
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if (ret)
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return ret;
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if (phy_common->mode == PHY_MODE_UFS_HS_B)
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is_rate_B = true;
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@ -147,6 +147,22 @@ struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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}
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EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
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int ufs_qcom_phy_get_reset(struct ufs_qcom_phy *phy_common)
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{
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struct reset_control *reset;
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if (phy_common->ufs_reset)
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return 0;
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reset = devm_reset_control_get_exclusive_by_index(phy_common->dev, 0);
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if (IS_ERR(reset))
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return PTR_ERR(reset);
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phy_common->ufs_reset = reset;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ufs_qcom_phy_get_reset);
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static int __ufs_qcom_phy_clk_get(struct device *dev,
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const char *name, struct clk **clk_out, bool err_print)
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{
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@ -533,6 +549,12 @@ int ufs_qcom_phy_power_on(struct phy *generic_phy)
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if (phy_common->is_powered_on)
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return 0;
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err = reset_control_deassert(phy_common->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to assert UFS PHY reset");
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return err;
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}
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if (!phy_common->is_started) {
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err = ufs_qcom_phy_start_serdes(phy_common);
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if (err)
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@ -620,6 +642,7 @@ int ufs_qcom_phy_power_off(struct phy *generic_phy)
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ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
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ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
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reset_control_assert(phy_common->ufs_reset);
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phy_common->is_powered_on = false;
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return 0;
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@ -261,11 +261,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
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if (is_rate_B)
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phy_set_mode(phy, PHY_MODE_UFS_HS_B);
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/* Assert PHY reset and apply PHY calibration values */
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ufs_qcom_assert_reset(hba);
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/* provide 1ms delay to let the reset pulse propagate */
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usleep_range(1000, 1100);
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/* phy initialization - calibrate the phy */
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ret = phy_init(phy);
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if (ret) {
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@ -274,15 +269,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
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goto out;
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}
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/* De-assert PHY reset and start serdes */
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ufs_qcom_deassert_reset(hba);
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/*
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* after reset deassertion, phy will need all ref clocks,
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* voltage, current to settle down before starting serdes.
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*/
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usleep_range(1000, 1100);
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/* power on phy - start serdes and phy's power and clocks */
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ret = phy_power_on(phy);
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if (ret) {
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@ -296,7 +282,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
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return 0;
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out_disable_phy:
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ufs_qcom_assert_reset(hba);
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phy_exit(phy);
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out:
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return ret;
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@ -559,9 +544,6 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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*/
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ufs_qcom_disable_lane_clks(host);
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phy_power_off(phy);
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/* Assert PHY soft reset */
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ufs_qcom_assert_reset(hba);
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goto out;
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}
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