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Dove: Fix Section mismatch warnings
Add missing __init markups to GPIO and timer functions. Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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parent
4d72cef17b
commit
ca2ac5cc95
2 changed files with 5 additions and 5 deletions
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@ -181,7 +181,7 @@ static int get_tclk(void)
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return 166666667;
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}
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static void dove_timer_init(void)
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static void __init dove_timer_init(void)
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{
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orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
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IRQ_DOVE_BRIDGE, get_tclk());
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@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
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/* Dump all the extra MPP registers. The platform code will dump the
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registers for pins 0-23. */
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static void dove_mpp_dump_regs(void)
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static void __init dove_mpp_dump_regs(void)
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{
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pr_debug("PMU_CTRL4_CTRL: %08x\n",
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readl(DOVE_MPP_CTRL4_VIRT_BASE));
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@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void)
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pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
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}
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static void dove_mpp_cfg_nfc(int sel)
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static void __init dove_mpp_cfg_nfc(int sel)
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{
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u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel)
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dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
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}
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static void dove_mpp_cfg_au1(int sel)
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static void __init dove_mpp_cfg_au1(int sel)
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{
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u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
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@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel)
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/* Configure the group registers, enabling GPIO if sel indicates the
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pin is to be used for GPIO */
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static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
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static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
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{
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u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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int gpio_mode;
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