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usb: dwc2: Add core parameter for service interval support
Added core parameter for service interval based scheduling. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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4 changed files with 18 additions and 0 deletions
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@ -416,6 +416,9 @@ enum dwc2_ep0_state {
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* back to DWC2_SPEED_PARAM_HIGH while device is gone.
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* 0 - No (default)
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* 1 - Yes
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* @service_interval: Enable service interval based scheduling.
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* 0 - No
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* 1 - Yes
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*
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* The following parameters may be specified when starting the module. These
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* parameters define how the DWC_otg controller should be configured. A
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@ -461,6 +464,7 @@ struct dwc2_core_params {
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bool lpm_clock_gating;
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bool besl;
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bool hird_threshold_en;
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bool service_interval;
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u8 hird_threshold;
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bool activate_stm_fs_transceiver;
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bool ipg_isoc_en;
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@ -605,6 +609,10 @@ struct dwc2_core_params {
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* FIFO sizing is enabled 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @service_interval_mode: For enabling service interval based scheduling in the
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* controller.
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* 0 - Disable
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* 1 - Enable
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*/
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struct dwc2_hw_params {
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unsigned op_mode:3;
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@ -635,6 +643,7 @@ struct dwc2_hw_params {
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unsigned utmi_phy_data_width:2;
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unsigned lpm_mode:1;
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unsigned ipg_isoc_en:1;
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unsigned service_interval_mode:1;
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u32 snpsid;
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u32 dev_ep_dirs;
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u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
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@ -701,6 +701,7 @@ static int params_show(struct seq_file *seq, void *v)
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print_param(seq, p, besl);
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print_param(seq, p, hird_threshold_en);
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print_param(seq, p, hird_threshold);
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print_param(seq, p, service_interval);
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print_param(seq, p, host_dma);
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print_param(seq, p, g_dma);
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print_param(seq, p, g_dma_desc);
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@ -3323,6 +3323,10 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
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}
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/* Enable Service Interval mode if supported */
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if (using_desc_dma(hsotg) && hsotg->params.service_interval)
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dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
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dwc2_writel(hsotg, 0, DAINTMSK);
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dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
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@ -299,6 +299,7 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
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p->hird_threshold_en = true;
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p->hird_threshold = 4;
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p->ipg_isoc_en = false;
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p->service_interval = false;
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p->max_packet_count = hw->max_packet_count;
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p->max_transfer_size = hw->max_transfer_size;
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
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@ -592,6 +593,7 @@ static void dwc2_check_params(struct dwc2_hsotg *hsotg)
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CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
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CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
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CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
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CHECK_BOOL(service_interval, hw->service_interval_mode);
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CHECK_RANGE(max_packet_count,
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15, hw->max_packet_count,
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hw->max_packet_count);
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@ -780,6 +782,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
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hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
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hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
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hw->service_interval_mode = !!(hwcfg4 &
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GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
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/* fifo sizes */
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hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
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