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habanalabs: support clock gating enable/disable
In Gaudi there is a feature of clock gating certain engines. Therefore, add this property to the device structure. In addition, due to a limitation of this feature, the driver needs to dynamically enable or disable this feature during run-time. Therefore, add ASIC interface functions to enable/disable this function from the common code. Moreover, this feature must be turned off when the user wishes to debug the ASIC by reading/writing registers and/or memory through the driver's debugfs. Therefore, add an option to enable/disable clock gating via the debugfs interface. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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803917f960
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6 changed files with 94 additions and 0 deletions
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@ -8,6 +8,16 @@ Description: Sets the device address to be used for read or write through
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only when the IOMMU is disabled.
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The acceptable value is a string that starts with "0x"
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What: /sys/kernel/debug/habanalabs/hl<n>/clk_gate
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Date: May 2020
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KernelVersion: 5.8
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Contact: oded.gabbay@gmail.com
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Description: Allow the root user to disable/enable in runtime the clock
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gating mechanism in Gaudi. Due to how Gaudi is built, the
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clock gating needs to be disabled in order to access the
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registers of the TPC and MME engines. This is sometimes needed
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during debug by the user and hence the user needs this option
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What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers
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Date: Jan 2019
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KernelVersion: 5.1
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@ -970,6 +970,55 @@ static ssize_t hl_device_write(struct file *f, const char __user *buf,
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return count;
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}
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static ssize_t hl_clk_gate_read(struct file *f, char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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char tmp_buf[200];
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ssize_t rc;
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if (*ppos)
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return 0;
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sprintf(tmp_buf, "%d\n", hdev->clock_gating);
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rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf,
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strlen(tmp_buf) + 1);
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return rc;
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}
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static ssize_t hl_clk_gate_write(struct file *f, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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u32 value;
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ssize_t rc;
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if (atomic_read(&hdev->in_reset)) {
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dev_warn_ratelimited(hdev->dev,
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"Can't change clock gating during reset\n");
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return 0;
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}
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rc = kstrtouint_from_user(buf, count, 10, &value);
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if (rc)
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return rc;
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if (value) {
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hdev->clock_gating = 1;
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if (hdev->asic_funcs->enable_clock_gating)
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hdev->asic_funcs->enable_clock_gating(hdev);
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} else {
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if (hdev->asic_funcs->disable_clock_gating)
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hdev->asic_funcs->disable_clock_gating(hdev);
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hdev->clock_gating = 0;
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}
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return count;
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}
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static ssize_t hl_stop_on_err_read(struct file *f, char __user *buf,
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size_t count, loff_t *ppos)
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{
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@ -1058,6 +1107,12 @@ static const struct file_operations hl_device_fops = {
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.write = hl_device_write
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};
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static const struct file_operations hl_clk_gate_fops = {
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.owner = THIS_MODULE,
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.read = hl_clk_gate_read,
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.write = hl_clk_gate_write
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};
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static const struct file_operations hl_stop_on_err_fops = {
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.owner = THIS_MODULE,
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.read = hl_stop_on_err_read,
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@ -1201,6 +1256,12 @@ void hl_debugfs_add_device(struct hl_device *hdev)
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dev_entry,
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&hl_device_fops);
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debugfs_create_file("clk_gate",
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0200,
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dev_entry->root,
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dev_entry,
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&hl_clk_gate_fops);
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debugfs_create_file("stop_on_err",
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0644,
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dev_entry->root,
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@ -603,6 +603,9 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable)
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hdev->in_debug = 0;
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if (!hdev->hard_reset_pending)
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hdev->asic_funcs->enable_clock_gating(hdev);
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goto out;
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}
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@ -613,6 +616,7 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable)
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goto out;
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}
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hdev->asic_funcs->disable_clock_gating(hdev);
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hdev->in_debug = 1;
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out:
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@ -5018,6 +5018,16 @@ int goya_armcp_info_get(struct hl_device *hdev)
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return 0;
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}
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static void goya_enable_clock_gating(struct hl_device *hdev)
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{
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}
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static void goya_disable_clock_gating(struct hl_device *hdev)
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{
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}
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static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
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struct seq_file *s)
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{
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@ -5239,6 +5249,8 @@ static const struct hl_asic_funcs goya_funcs = {
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.mmu_invalidate_cache = goya_mmu_invalidate_cache,
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.mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
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.send_heartbeat = goya_send_heartbeat,
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.enable_clock_gating = goya_enable_clock_gating,
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.disable_clock_gating = goya_disable_clock_gating,
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.debug_coresight = goya_debug_coresight,
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.is_device_idle = goya_is_device_idle,
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.soft_reset_late_init = goya_soft_reset_late_init,
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@ -578,6 +578,8 @@ enum hl_pll_frequency {
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* @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
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* ASID-VA-size mask.
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* @send_heartbeat: send is-alive packet to ArmCP and verify response.
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* @enable_clock_gating: enable clock gating for reducing power consumption.
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* @disable_clock_gating: disable clock for accessing registers on HBW.
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* @debug_coresight: perform certain actions on Coresight for debugging.
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* @is_device_idle: return true if device is idle, false otherwise.
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* @soft_reset_late_init: perform certain actions needed after soft reset.
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@ -678,6 +680,8 @@ struct hl_asic_funcs {
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void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
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u32 asid, u64 va, u64 size);
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int (*send_heartbeat)(struct hl_device *hdev);
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void (*enable_clock_gating)(struct hl_device *hdev);
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void (*disable_clock_gating)(struct hl_device *hdev);
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int (*debug_coresight)(struct hl_device *hdev, void *data);
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bool (*is_device_idle)(struct hl_device *hdev, u32 *mask,
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struct seq_file *s);
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@ -1408,6 +1412,7 @@ struct hl_device_idle_busy_ts {
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* huge pages.
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* @init_done: is the initialization of the device done.
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* @mmu_enable: is MMU enabled.
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* @clock_gating: is clock gating enabled.
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* @device_cpu_disabled: is the device CPU disabled (due to timeouts)
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* @dma_mask: the dma mask that was set for this device
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* @in_debug: is device under debug. This, together with fpriv_list, enforces
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@ -1494,6 +1499,7 @@ struct hl_device {
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u8 dram_default_page_mapping;
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u8 pmmu_huge_range;
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u8 init_done;
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u8 clock_gating;
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u8 device_cpu_disabled;
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u8 dma_mask;
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u8 in_debug;
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@ -231,6 +231,7 @@ static void set_driver_behavior_per_device(struct hl_device *hdev)
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hdev->fw_loading = 1;
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hdev->cpu_queues_enable = 1;
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hdev->heartbeat = 1;
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hdev->clock_gating = 1;
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hdev->reset_pcilink = 0;
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}
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