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[SPARC]: Remove the broken SUN_AURORA driver.
The SUN_AURORA driver: - has been marked as BROKEN for more than two years and - is still marked as BROKEN. Drivers that had been marked as BROKEN for such a long time seem to be unlikely to be revived in the forseeable future. But if anyone wants to ever revive this driver, the code is still present in the older kernel releases. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Adrian Bunk
David S. Miller
parent
2a786b452e
commit
cacfd56756
6 changed files with 0 additions and 2889 deletions
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@ -65,7 +65,6 @@ CMAGIC 0x0111 user include/linux/a.out.h
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MKISS_DRIVER_MAGIC 0x04bf mkiss_channel drivers/net/mkiss.h
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RISCOM8_MAGIC 0x0907 riscom_port drivers/char/riscom8.h
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SPECIALIX_MAGIC 0x0907 specialix_port drivers/char/specialix_io8.h
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AURORA_MAGIC 0x0A18 Aurora_port drivers/sbus/char/aurora.h
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HDLC_MAGIC 0x239e n_hdlc drivers/char/n_hdlc.c
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APM_BIOS_MAGIC 0x4101 apm_user arch/i386/kernel/apm.c
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CYCLADES_MAGIC 0x4359 cyclades_port include/linux/cyclades.h
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@ -46,13 +46,6 @@ config SUN_VIDEOPIX
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based on the Phillips SAA9051, can handle NTSC and PAL/SECAM and
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SVIDEO signals.
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config SUN_AURORA
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tristate "Aurora Multiboard 1600se (EXPERIMENTAL)"
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depends on EXPERIMENTAL && BROKEN
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help
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The Aurora Multiboard is a multi-port high-speed serial controller.
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If you have one of these, say Y.
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config TADPOLE_TS102_UCTRL
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tristate "Tadpole TS102 Microcontroller support (EXPERIMENTAL)"
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depends on EXPERIMENTAL && SPARC32
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@ -19,7 +19,6 @@ obj-$(CONFIG_SUN_OPENPROMIO) += openprom.o
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obj-$(CONFIG_SUN_MOSTEK_RTC) += rtc.o
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obj-$(CONFIG_SUN_BPP) += bpp.o
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obj-$(CONFIG_SUN_VIDEOPIX) += vfc.o
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obj-$(CONFIG_SUN_AURORA) += aurora.o
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obj-$(CONFIG_TADPOLE_TS102_UCTRL) += uctrl.o
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obj-$(CONFIG_SUN_JSFLASH) += jsflash.o
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obj-$(CONFIG_BBC_I2C) += bbc.o
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File diff suppressed because it is too large
Load diff
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@ -1,276 +0,0 @@
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/* $Id: aurora.h,v 1.6 2001/06/05 12:23:38 davem Exp $
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* linux/drivers/sbus/char/aurora.h -- Aurora multiport driver
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*
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* Copyright (c) 1999 by Oliver Aldulea (oli@bv.ro)
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*
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* This code is based on the RISCom/8 multiport serial driver written
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* by Dmitry Gorodchanin (pgmdsg@ibi.com), based on the Linux serial
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* driver, written by Linus Torvalds, Theodore T'so and others.
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* The Aurora multiport programming info was obtained mainly from the
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* Cirrus Logic CD180 documentation (available on the web), and by
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* doing heavy tests on the board. Many thanks to Eddie C. Dost for the
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* help on the sbus interface.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Revision 1.0
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*
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* This is the first public release.
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*
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* This version needs a lot of feedback. This is the version that works
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* with _my_ board. My board is model 1600se, revision '@(#)1600se.fth
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* 1.2 3/28/95 1'. The driver might work with your board, but I do not
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* guarantee it. If you have _any_ type of board, I need to know if the
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* driver works or not, I need to know exactly your board parameters
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* (get them with 'cd /proc/openprom/iommu/sbus/sio16/; ls *; cat *')
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* Also, I need your board revision code, which is written on the board.
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* Send me the output of my driver too (it outputs through klogd).
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*
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* If the driver does not work, you can try enabling the debug options
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* to see what's wrong or what should be done.
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*
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* I'm sorry about the alignment of the code. It was written in a
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* 128x48 environment.
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*
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* I must say that I do not like Aurora Technologies' policy. I asked
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* them to help me do this driver faster, but they ended by something
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* like "don't call us, we'll call you", and I never heard anything
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* from them. They told me "knowing the way the board works, I don't
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* doubt you and others on the net will make the driver."
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* The truth about this board is that it has nothing intelligent on it.
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* If you want to say to somebody what kind of board you have, say that
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* it uses Cirrus Logic processors (CD180). The power of the board is
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* in those two chips. The rest of the board is the interface to the
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* sbus and to the peripherals. Still, they did something smart: they
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* reversed DTR and RTS to make on-board automatic hardware flow
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* control usable.
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* Thanks to Aurora Technologies for wasting my time, nerves and money.
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*/
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#ifndef __LINUX_AURORA_H
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#define __LINUX_AURORA_H
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#include <linux/serial.h>
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#include <linux/serialP.h>
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#ifdef __KERNEL__
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/* This is the number of boards to support. I've only tested this driver with
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* one board, so it might not work.
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*/
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#define AURORA_NBOARD 1
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/* Useful ? Yes. But you can safely comment the warnings if they annoy you
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* (let me say that again: the warnings in the code, not this define).
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*/
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#define AURORA_PARANOIA_CHECK
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/* Well, after many lost nights, I found that the IRQ for this board is
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* selected from four built-in values by writing some bits in the
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* configuration register. This causes a little problem to occur: which
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* IRQ to select ? Which one is the best for the user ? Well, I finally
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* decided for the following algorithm: if the "bintr" value is not acceptable
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* (not within type_1_irq[], then test the "intr" value, if that fails too,
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* try each value from type_1_irq until succeded. Hope it's ok.
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* You can safely reorder the irq's.
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*/
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#define TYPE_1_IRQS 4
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unsigned char type_1_irq[TYPE_1_IRQS] = {
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3, 5, 9, 13
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};
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/* I know something about another method of interrupt setting, but not enough.
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* Also, this is for another type of board, so I first have to learn how to
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* detect it.
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#define TYPE_2_IRQS 3
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unsigned char type_2_irq[TYPE_2_IRQS] = {
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0, 0, 0 ** could anyone find these for me ? (see AURORA_ALLIRQ below) **
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};
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unsigned char type_2_mask[TYPE_2_IRQS] = {
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32, 64, 128
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};
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*/
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/* The following section should only be modified by those who know what
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* they're doing (or don't, but want to help with some feedback). Modifying
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* anything raises a _big_ probability for your system to hang, but the
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* sacrifice worths. (I sacrificed my ext2fs many, many times...)
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*/
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/* This one tries to dump to console the name of almost every function called,
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* and many other debugging info.
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*/
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#undef AURORA_DEBUG
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/* These are the most dangerous and useful defines. They do printk() during
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* the interrupt processing routine(s), so if you manage to get "flooded" by
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* irq's, start thinking about the "Power off/on" button...
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*/
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#undef AURORA_INTNORM /* This one enables the "normal" messages, but some
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* of them cause flood, so I preffered putting
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* them under a define */
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#undef AURORA_INT_DEBUG /* This one is really bad. */
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/* Here's something helpful: after n irq's, the board will be disabled. This
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* prevents irq flooding during debug (no need to think about power
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* off/on anymore...)
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*/
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#define AURORA_FLOODPRO 10
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/* This one helps finding which irq the board calls, in case of a strange/
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* unsupported board. AURORA_INT_DEBUG should be enabled, because I don't
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* think /proc/interrupts or any command will be available in case of an irq
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* flood... "allirq" is the list of all free irq's.
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*/
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/*
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#define AURORA_ALLIRQ 6
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int allirq[AURORA_ALLIRQ]={
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2,3,5,7,9,13
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};
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*/
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/* These must not be modified. These values are assumed during the code for
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* performance optimisations.
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*/
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#define AURORA_NCD180 2 /* two chips per board */
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#define AURORA_NPORT 8 /* 8 ports per chip */
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/* several utilities */
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#define AURORA_BOARD(line) (((line) >> 4) & 0x01)
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#define AURORA_CD180(line) (((line) >> 3) & 0x01)
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#define AURORA_PORT(line) ((line) & 15)
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#define AURORA_TNPORTS (AURORA_NBOARD*AURORA_NCD180*AURORA_NPORT)
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/* Ticks per sec. Used for setting receiver timeout and break length */
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#define AURORA_TPS 4000
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#define AURORA_MAGIC 0x0A18
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/* Yeah, after heavy testing I decided it must be 6.
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* Sure, You can change it if needed.
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*/
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#define AURORA_RXFIFO 6 /* Max. receiver FIFO size (1-8) */
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#define AURORA_RXTH 7
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struct aurora_reg1 {
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__volatile__ unsigned char r;
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};
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struct aurora_reg128 {
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__volatile__ unsigned char r[128];
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};
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struct aurora_reg4 {
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__volatile__ unsigned char r[4];
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};
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struct Aurora_board {
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unsigned long flags;
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struct aurora_reg1 * r0; /* This is the board configuration
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* register (write-only). */
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struct aurora_reg128 * r[2]; /* These are the registers for the
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* two chips. */
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struct aurora_reg4 * r3; /* These are used for hardware-based
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* acknowledge. Software-based ack is
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* not supported by CD180. */
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unsigned int oscfreq; /* The on-board oscillator
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* frequency, in Hz. */
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unsigned char irq;
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#ifdef MODULE
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signed char count; /* counts the use of the board */
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#endif
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/* Values for the dtr_rts swapped mode. */
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unsigned char DTR;
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unsigned char RTS;
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unsigned char MSVDTR;
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unsigned char MSVRTS;
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/* Values for hardware acknowledge. */
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unsigned char ACK_MINT, ACK_TINT, ACK_RINT;
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};
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/* Board configuration register */
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#define AURORA_CFG_ENABLE_IO 8
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#define AURORA_CFG_ENABLE_IRQ 4
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/* Board flags */
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#define AURORA_BOARD_PRESENT 0x00000001
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#define AURORA_BOARD_ACTIVE 0x00000002
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#define AURORA_BOARD_TYPE_2 0x00000004 /* don't know how to
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* detect this yet */
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#define AURORA_BOARD_DTR_FLOW_OK 0x00000008
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/* The story goes like this: Cirrus programmed the CD-180 chip to do automatic
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* hardware flow control, and do it using CTS and DTR. CTS is ok, but, if you
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* have a modem and the chip drops DTR, then the modem will drop the carrier
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* (ain't that cute...). Luckily, the guys at Aurora decided to swap DTR and
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* RTS, which makes the flow control usable. I hope that all the boards made
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* by Aurora have these two signals swapped. If your's doesn't but you have a
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* breakout box, you can try to reverse them yourself, then set the following
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* flag.
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*/
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#undef AURORA_FORCE_DTR_FLOW
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/* In fact, a few more words have to be said about hardware flow control.
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* This driver handles "output" flow control through the on-board facility
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* CTS Auto Enable. For the "input" flow control there are two cases when
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* the flow should be controlled. The first case is when the kernel is so
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* busy that it cannot process IRQ's in time; this flow control can only be
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* activated by the on-board chip, and if the board has RTS and DTR swapped,
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* this facility is usable. The second case is when the application is so
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* busy that it cannot receive bytes from the kernel, and this flow must be
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* activated by software. This second case is not yet implemented in this
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* driver. Unfortunately, I estimate that the second case is the one that
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* occurs the most.
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*/
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struct Aurora_port {
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int magic;
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int baud_base;
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int flags;
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struct tty_struct * tty;
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int count;
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int blocked_open;
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long event;
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int timeout;
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int close_delay;
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unsigned char * xmit_buf;
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int custom_divisor;
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int xmit_head;
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int xmit_tail;
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int xmit_cnt;
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wait_queue_head_t open_wait;
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wait_queue_head_t close_wait;
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struct tq_struct tqueue;
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struct tq_struct tqueue_hangup;
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short wakeup_chars;
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short break_length;
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unsigned short closing_wait;
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unsigned char mark_mask;
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unsigned char SRER;
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unsigned char MSVR;
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unsigned char COR2;
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#ifdef AURORA_REPORT_OVERRUN
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unsigned long overrun;
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#endif
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#ifdef AURORA_REPORT_FIFO
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unsigned long hits[10];
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#endif
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};
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#endif
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#endif /*__LINUX_AURORA_H*/
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@ -1,240 +0,0 @@
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/* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */
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#define CD180_NCH 8 /* Total number of channels */
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#define CD180_TPC 16 /* Ticks per character */
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#define CD180_NFIFO 8 /* TX FIFO size */
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/* Global registers */
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#define CD180_GFRCR 0x6b /* Global Firmware Revision Code Register */
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#define CD180_SRCR 0x66 /* Service Request Configuration Register */
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#define CD180_PPRH 0x70 /* Prescaler Period Register High */
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#define CD180_PPRL 0x71 /* Prescaler Period Register Low */
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#define CD180_MSMR 0x61 /* Modem Service Match Register */
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#define CD180_TSMR 0x62 /* Transmit Service Match Register */
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#define CD180_RSMR 0x63 /* Receive Service Match Register */
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#define CD180_GSVR 0x40 /* Global Service Vector Register */
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#define CD180_SRSR 0x65 /* Service Request Status Register */
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#define CD180_GSCR 0x41 /* Global Service Channel Register */
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#define CD180_CAR 0x64 /* Channel Access Register */
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/* Indexed registers */
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#define CD180_RDCR 0x07 /* Receive Data Count Register */
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#define CD180_RDR 0x78 /* Receiver Data Register */
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#define CD180_RCSR 0x7a /* Receiver Character Status Register */
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#define CD180_TDR 0x7b /* Transmit Data Register */
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#define CD180_EOSRR 0x7f /* End of Service Request Register */
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/* Channel Registers */
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#define CD180_SRER 0x02 /* Service Request Enable Register */
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#define CD180_CCR 0x01 /* Channel Command Register */
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#define CD180_COR1 0x03 /* Channel Option Register 1 */
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#define CD180_COR2 0x04 /* Channel Option Register 2 */
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#define CD180_COR3 0x05 /* Channel Option Register 3 */
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#define CD180_CCSR 0x06 /* Channel Control Status Register */
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#define CD180_RTPR 0x18 /* Receive Timeout Period Register */
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#define CD180_RBPRH 0x31 /* Receive Bit Rate Period Register High */
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#define CD180_RBPRL 0x32 /* Receive Bit Rate Period Register Low */
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#define CD180_TBPRH 0x39 /* Transmit Bit Rate Period Register High */
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#define CD180_TBPRL 0x3a /* Transmit Bit Rate Period Register Low */
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#define CD180_SCHR1 0x09 /* Special Character Register 1 */
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#define CD180_SCHR2 0x0a /* Special Character Register 2 */
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#define CD180_SCHR3 0x0b /* Special Character Register 3 */
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#define CD180_SCHR4 0x0c /* Special Character Register 4 */
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#define CD180_MCR 0x12 /* Modem Change Register */
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#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
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#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
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#define CD180_MSVR 0x28 /* Modem Signal Value Register */
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#define CD180_MSVRTS 0x29 /* Modem Signal Value RTS */
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#define CD180_MSVDTR 0x2a /* Modem Signal Value DTR */
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/* Global Interrupt Vector Register (R/W) */
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#define GSVR_ITMASK 0x07 /* Interrupt type mask */
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#define GSVR_IT_MDM 0x01 /* Modem Signal Change Interrupt */
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#define GSVR_IT_TX 0x02 /* Transmit Data Interrupt */
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#define GSVR_IT_RGD 0x03 /* Receive Good Data Interrupt */
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#define GSVR_IT_REXC 0x07 /* Receive Exception Interrupt */
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/* Global Interrupt Channel Register (R/W) */
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#define GSCR_CHAN 0x1c /* Channel Number Mask */
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#define GSCR_CHAN_OFF 2 /* Channel Number Offset */
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/* Channel Address Register (R/W) */
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#define CAR_CHAN 0x07 /* Channel Number Mask */
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/* Receive Character Status Register (R/O) */
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#define RCSR_TOUT 0x80 /* Rx Timeout */
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#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
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#define RCSR_NO_SC 0x00 /* No Special Characters Detected */
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#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
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#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
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#define RCSR_SC_3 0x30 /* Special Char 3 Detected */
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#define RCSR_SC_4 0x40 /* Special Char 4 Detected */
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#define RCSR_BREAK 0x08 /* Break has been detected */
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#define RCSR_PE 0x04 /* Parity Error */
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#define RCSR_FE 0x02 /* Frame Error */
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#define RCSR_OE 0x01 /* Overrun Error */
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/* Channel Command Register (R/W) (commands in groups can be OR-ed) */
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#define CCR_HARDRESET 0x81 /* Reset the chip */
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#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
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||||
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||||
#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
|
||||
#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
|
||||
#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
|
||||
|
||||
#define CCR_SSCH1 0x21 /* Send Special Character 1 */
|
||||
|
||||
#define CCR_SSCH2 0x22 /* Send Special Character 2 */
|
||||
|
||||
#define CCR_SSCH3 0x23 /* Send Special Character 3 */
|
||||
|
||||
#define CCR_SSCH4 0x24 /* Send Special Character 4 */
|
||||
|
||||
#define CCR_TXEN 0x18 /* Enable Transmitter */
|
||||
#define CCR_RXEN 0x12 /* Enable Receiver */
|
||||
|
||||
#define CCR_TXDIS 0x14 /* Disable Transmitter */
|
||||
#define CCR_RXDIS 0x11 /* Disable Receiver */
|
||||
|
||||
|
||||
/* Service Request Enable Register (R/W) */
|
||||
|
||||
#define SRER_DSR 0x80 /* Enable interrupt on DSR change */
|
||||
#define SRER_CD 0x40 /* Enable interrupt on CD change */
|
||||
#define SRER_CTS 0x20 /* Enable interrupt on CTS change */
|
||||
#define SRER_RXD 0x10 /* Enable interrupt on Receive Data */
|
||||
#define SRER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
|
||||
#define SRER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
|
||||
#define SRER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
|
||||
#define SRER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
|
||||
|
||||
|
||||
/* Channel Option Register 1 (R/W) */
|
||||
|
||||
#define COR1_ODDP 0x80 /* Odd Parity */
|
||||
#define COR1_PARMODE 0x60 /* Parity Mode mask */
|
||||
#define COR1_NOPAR 0x00 /* No Parity */
|
||||
#define COR1_FORCEPAR 0x20 /* Force Parity */
|
||||
#define COR1_NORMPAR 0x40 /* Normal Parity */
|
||||
#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
|
||||
#define COR1_STOPBITS 0x0c /* Number of Stop Bits */
|
||||
#define COR1_1SB 0x00 /* 1 Stop Bit */
|
||||
#define COR1_15SB 0x04 /* 1.5 Stop Bits */
|
||||
#define COR1_2SB 0x08 /* 2 Stop Bits */
|
||||
#define COR1_CHARLEN 0x03 /* Character Length */
|
||||
#define COR1_5BITS 0x00 /* 5 bits */
|
||||
#define COR1_6BITS 0x01 /* 6 bits */
|
||||
#define COR1_7BITS 0x02 /* 7 bits */
|
||||
#define COR1_8BITS 0x03 /* 8 bits */
|
||||
|
||||
|
||||
/* Channel Option Register 2 (R/W) */
|
||||
|
||||
#define COR2_IXM 0x80 /* Implied XON mode */
|
||||
#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
|
||||
#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
|
||||
#define COR2_LLM 0x10 /* Local Loopback Mode */
|
||||
#define COR2_RLM 0x08 /* Remote Loopback Mode */
|
||||
#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
|
||||
#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
|
||||
#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
|
||||
|
||||
|
||||
/* Channel Option Register 3 (R/W) */
|
||||
|
||||
#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
|
||||
#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
|
||||
#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
|
||||
#define COR3_SCDE 0x10 /* Special Character Detection Enable */
|
||||
#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
|
||||
|
||||
|
||||
/* Channel Control Status Register (R/O) */
|
||||
|
||||
#define CCSR_RXEN 0x80 /* Receiver Enabled */
|
||||
#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
|
||||
#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
|
||||
#define CCSR_TXEN 0x08 /* Transmitter Enabled */
|
||||
#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
|
||||
#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
|
||||
|
||||
|
||||
/* Modem Change Option Register 1 (R/W) */
|
||||
|
||||
#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
|
||||
#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
|
||||
#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
|
||||
#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
|
||||
#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
|
||||
|
||||
|
||||
/* Modem Change Option Register 2 (R/W) */
|
||||
|
||||
#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
|
||||
#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
|
||||
#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
|
||||
|
||||
|
||||
/* Modem Change Register (R/W) */
|
||||
|
||||
#define MCR_DSRCHG 0x80 /* DSR Changed */
|
||||
#define MCR_CDCHG 0x40 /* CD Changed */
|
||||
#define MCR_CTSCHG 0x20 /* CTS Changed */
|
||||
|
||||
|
||||
/* Modem Signal Value Register (R/W) */
|
||||
|
||||
#define MSVR_DSR 0x80 /* Current state of DSR input */
|
||||
#define MSVR_CD 0x40 /* Current state of CD input */
|
||||
#define MSVR_CTS 0x20 /* Current state of CTS input */
|
||||
#define MSVR_DTR 0x02 /* Current state of DTR output */
|
||||
#define MSVR_RTS 0x01 /* Current state of RTS output */
|
||||
|
||||
|
||||
/* Service Request Status Register */
|
||||
|
||||
#define SRSR_CMASK 0xC0 /* Current Service Context Mask */
|
||||
#define SRSR_CNONE 0x00 /* Not in a service context */
|
||||
#define SRSR_CRX 0x40 /* Rx Context */
|
||||
#define SRSR_CTX 0x80 /* Tx Context */
|
||||
#define SRSR_CMDM 0xC0 /* Modem Context */
|
||||
#define SRSR_ANYINT 0x6F /* Any interrupt flag */
|
||||
#define SRSR_RINT 0x10 /* Receive Interrupt */
|
||||
#define SRSR_TINT 0x04 /* Transmit Interrupt */
|
||||
#define SRSR_MINT 0x01 /* Modem Interrupt */
|
||||
#define SRSR_REXT 0x20 /* Receive External Interrupt */
|
||||
#define SRSR_TEXT 0x08 /* Transmit External Interrupt */
|
||||
#define SRSR_MEXT 0x02 /* Modem External Interrupt */
|
||||
|
||||
|
||||
/* Service Request Configuration Register */
|
||||
|
||||
#define SRCR_PKGTYPE 0x80
|
||||
#define SRCR_REGACKEN 0x40
|
||||
#define SRCR_DAISYEN 0x20
|
||||
#define SRCR_GLOBPRI 0x10
|
||||
#define SRCR_UNFAIR 0x08
|
||||
#define SRCR_AUTOPRI 0x02
|
||||
#define SRCR_PRISEL 0x01
|
||||
|
||||
/* Values for register-based Interrupt ACKs */
|
||||
#define CD180_ACK_MINT 0x75 /* goes to MSMR */
|
||||
#define CD180_ACK_TINT 0x76 /* goes to TSMR */
|
||||
#define CD180_ACK_RINT 0x77 /* goes to RSMR */
|
||||
|
||||
/* Escape characters */
|
||||
|
||||
#define CD180_C_ESC 0x00 /* Escape character */
|
||||
#define CD180_C_SBRK 0x81 /* Start sending BREAK */
|
||||
#define CD180_C_DELAY 0x82 /* Delay output */
|
||||
#define CD180_C_EBRK 0x83 /* Stop sending BREAK */
|
||||
Loading…
Reference in a new issue