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drm/exynos: add ipp subsystem 

This patch adds Image Post Processing(IPP) support for exynos drm driver.

IPP supports image scaler/rotator and input/output DMA operations
using IPP subsystem framework to control FIMC, Rotator and GSC hardware
and supports some user interfaces for user side.

And each IPP-based drivers support Memory to Memory operations
with various converting. And in case of FIMC hardware, it also supports
Writeback and Display output operations through local path.

Features:
- Memory to Memory operation support.
- Various pixel formats support.
- Image scaling support.
- Color Space Conversion support.
- Image crop operation support.
- Rotate operation support to 90, 180 or 270 degree.
- Flip operation support to vertical, horizontal or both.
- Writeback operation support to display blended image of FIMD fifo on screen

A summary to IPP Subsystem operations:
First of all, user should get property capabilities from IPP subsystem
and set these properties to hardware registers for desired operations.
The properties could be pixel format, position, rotation degree and
flip operation.

And next, user should set source and destination buffer data using
DRM_EXYNOS_IPP_QUEUE_BUF ioctl command with gem handles to source and
destinition buffers.

And next, user can control user-desired hardware with desired operations
such as play, stop, pause and resume controls.

And finally, user can aware of dma operation completion and also get
destination buffer that it contains user-desried result through dequeue
command.

IOCTL commands:
- DRM_EXYNOS_IPP_GET_PROPERTY
  . get ipp driver capabilitis and id.
- DRM_EXYNOS_IPP_SET_PROPERTY
  . set format, position, rotation, flip to source and destination buffers
- DRM_EXYNOS_IPP_QUEUE_BUF
  . enqueue/dequeue buffer and make event list.
- DRM_EXYNOS_IPP_CMD_CTRL
  . play/stop/pause/resume control.

Event:
- DRM_EXYNOS_IPP_EVENT
  . a event to notify dma operation completion to user side.

Basic control flow:
Open -> Get properties -> User choose desired IPP sub driver(FIMC, Rotator
or GSCALER) -> Set Property -> Create gem handle -> Enqueue to source and
destination buffers -> Command control(Play) -> Event is notified to User
-> User gets destinition buffer complated -> (Enqueue to source and
destination buffers -> Event is notified to User) * N -> Queue/Dequeue to
source and destination buffers -> Command control(Stop) -> Free gem handle
-> Close

Changelog v1 ~ v5:
- added comments, code fixups and cleanups.

Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Eunchul Kim 2012-12-14 18:10:31 +09:00 committed by Inki Dae
parent d636ead86f
commit cb471f14b5
7 changed files with 2536 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/exynos/Kconfig
View File

@ -45,3 +45,9 @@ config DRM_EXYNOS_G2D
depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_G2D
help
Choose this option if you want to use Exynos G2D for DRM.
config DRM_EXYNOS_IPP
bool "Exynos DRM IPP"
depends on DRM_EXYNOS
help
Choose this option if you want to use IPP feature for DRM.

1
drivers/gpu/drm/exynos/Makefile
View File

@ -16,5 +16,6 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynos_mixer.o \
exynos_drm_hdmi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_G2D) += exynos_drm_g2d.o
exynosdrm-$(CONFIG_DRM_EXYNOS_IPP) += exynos_drm_ipp.o
obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o

24
drivers/gpu/drm/exynos/exynos_drm_drv.c
View File

@ -40,6 +40,7 @@
#include "exynos_drm_vidi.h"
#include "exynos_drm_dmabuf.h"
#include "exynos_drm_g2d.h"
#include "exynos_drm_ipp.h"
#include "exynos_drm_iommu.h"
#define DRIVER_NAME "exynos"
@ -249,6 +250,14 @@ static struct drm_ioctl_desc exynos_ioctls[] = {
exynos_g2d_set_cmdlist_ioctl, DRM_UNLOCKED | DRM_AUTH),
DRM_IOCTL_DEF_DRV(EXYNOS_G2D_EXEC,
exynos_g2d_exec_ioctl, DRM_UNLOCKED | DRM_AUTH),
DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_PROPERTY,
exynos_drm_ipp_get_property, DRM_UNLOCKED | DRM_AUTH),
DRM_IOCTL_DEF_DRV(EXYNOS_IPP_SET_PROPERTY,
exynos_drm_ipp_set_property, DRM_UNLOCKED | DRM_AUTH),
DRM_IOCTL_DEF_DRV(EXYNOS_IPP_QUEUE_BUF,
exynos_drm_ipp_queue_buf, DRM_UNLOCKED | DRM_AUTH),
DRM_IOCTL_DEF_DRV(EXYNOS_IPP_CMD_CTRL,
exynos_drm_ipp_cmd_ctrl, DRM_UNLOCKED | DRM_AUTH),
};
static const struct file_operations exynos_drm_driver_fops = {
@ -363,6 +372,12 @@ static int __init exynos_drm_init(void)
goto out_g2d;
#endif
#ifdef CONFIG_DRM_EXYNOS_IPP
ret = platform_driver_register(&ipp_driver);
if (ret < 0)
goto out_ipp;
#endif
ret = platform_driver_register(&exynos_drm_platform_driver);
if (ret < 0)
goto out_drm;
@ -380,6 +395,11 @@ out:
platform_driver_unregister(&exynos_drm_platform_driver);
out_drm:
#ifdef CONFIG_DRM_EXYNOS_IPP
platform_driver_unregister(&ipp_driver);
out_ipp:
#endif
#ifdef CONFIG_DRM_EXYNOS_G2D
platform_driver_unregister(&g2d_driver);
out_g2d:
@ -416,6 +436,10 @@ static void __exit exynos_drm_exit(void)
platform_driver_unregister(&exynos_drm_platform_driver);
#ifdef CONFIG_DRM_EXYNOS_IPP
platform_driver_unregister(&ipp_driver);
#endif
#ifdef CONFIG_DRM_EXYNOS_G2D
platform_driver_unregister(&g2d_driver);
#endif

7
drivers/gpu/drm/exynos/exynos_drm_drv.h
View File

@ -232,8 +232,14 @@ struct exynos_drm_g2d_private {
struct list_head userptr_list;
};
struct exynos_drm_ipp_private {
struct device *dev;
struct list_head event_list;
};
struct drm_exynos_file_private {
struct exynos_drm_g2d_private *g2d_priv;
struct exynos_drm_ipp_private *ipp_priv;
};
/*
@ -343,4 +349,5 @@ extern struct platform_driver mixer_driver;
extern struct platform_driver exynos_drm_common_hdmi_driver;
extern struct platform_driver vidi_driver;
extern struct platform_driver g2d_driver;
extern struct platform_driver ipp_driver;
#endif

2042
drivers/gpu/drm/exynos/exynos_drm_ipp.c Normal file
View File

File diff suppressed because it is too large Load Diff

266
drivers/gpu/drm/exynos/exynos_drm_ipp.h Normal file
View File

@ -0,0 +1,266 @@
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
*
* Authors:
* Eunchul Kim <chulspro.kim@samsung.com>
* Jinyoung Jeon <jy0.jeon@samsung.com>
* Sangmin Lee <lsmin.lee@samsung.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _EXYNOS_DRM_IPP_H_
#define _EXYNOS_DRM_IPP_H_
#define for_each_ipp_ops(pos) \
for (pos = 0; pos < EXYNOS_DRM_OPS_MAX; pos++)
#define for_each_ipp_planar(pos) \
for (pos = 0; pos < EXYNOS_DRM_PLANAR_MAX; pos++)
#define IPP_GET_LCD_WIDTH _IOR('F', 302, int)
#define IPP_GET_LCD_HEIGHT _IOR('F', 303, int)
#define IPP_SET_WRITEBACK _IOW('F', 304, u32)
/* definition of state */
enum drm_exynos_ipp_state {
IPP_STATE_IDLE,
IPP_STATE_START,
IPP_STATE_STOP,
};
/*
* A structure of command work information.
* @work: work structure.
* @ippdrv: current work ippdrv.
* @c_node: command node information.
* @ctrl: command control.
*/
struct drm_exynos_ipp_cmd_work {
struct work_struct work;
struct exynos_drm_ippdrv *ippdrv;
struct drm_exynos_ipp_cmd_node *c_node;
enum drm_exynos_ipp_ctrl ctrl;
};
/*
* A structure of command node.
*
* @priv: IPP private infomation.
* @list: list head to command queue information.
* @event_list: list head of event.
* @mem_list: list head to source,destination memory queue information.
* @cmd_lock: lock for synchronization of access to ioctl.
* @mem_lock: lock for synchronization of access to memory nodes.
* @event_lock: lock for synchronization of access to scheduled event.
* @start_complete: completion of start of command.
* @stop_complete: completion of stop of command.
* @property: property information.
* @start_work: start command work structure.
* @stop_work: stop command work structure.
* @event_work: event work structure.
* @state: state of command node.
*/
struct drm_exynos_ipp_cmd_node {
struct exynos_drm_ipp_private *priv;
struct list_head list;
struct list_head event_list;
struct list_head mem_list[EXYNOS_DRM_OPS_MAX];
struct mutex cmd_lock;
struct mutex mem_lock;
struct mutex event_lock;
struct completion start_complete;
struct completion stop_complete;
struct drm_exynos_ipp_property property;
struct drm_exynos_ipp_cmd_work *start_work;
struct drm_exynos_ipp_cmd_work *stop_work;
struct drm_exynos_ipp_event_work *event_work;
enum drm_exynos_ipp_state state;
};
/*
* A structure of buffer information.
*
* @gem_objs: Y, Cb, Cr each gem object.
* @base: Y, Cb, Cr each planar address.
*/
struct drm_exynos_ipp_buf_info {
unsigned long handles[EXYNOS_DRM_PLANAR_MAX];
dma_addr_t base[EXYNOS_DRM_PLANAR_MAX];
};
/*
* A structure of wb setting infomation.
*
* @enable: enable flag for wb.
* @refresh: HZ of the refresh rate.
*/
struct drm_exynos_ipp_set_wb {
__u32 enable;
__u32 refresh;
};
/*
* A structure of event work information.
*
* @work: work structure.
* @ippdrv: current work ippdrv.
* @buf_id: id of src, dst buffer.
*/
struct drm_exynos_ipp_event_work {
struct work_struct work;
struct exynos_drm_ippdrv *ippdrv;
u32 buf_id[EXYNOS_DRM_OPS_MAX];
};
/*
* A structure of source,destination operations.
*
* @set_fmt: set format of image.
* @set_transf: set transform(rotations, flip).
* @set_size: set size of region.
* @set_addr: set address for dma.
*/
struct exynos_drm_ipp_ops {
int (*set_fmt)(struct device *dev, u32 fmt);
int (*set_transf)(struct device *dev,
enum drm_exynos_degree degree,
enum drm_exynos_flip flip, bool *swap);
int (*set_size)(struct device *dev, int swap,
struct drm_exynos_pos *pos, struct drm_exynos_sz *sz);
int (*set_addr)(struct device *dev,
struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
enum drm_exynos_ipp_buf_type buf_type);
};
/*
* A structure of ipp driver.
*
* @drv_list: list head for registed sub driver information.
* @parent_dev: parent device information.
* @dev: platform device.
* @drm_dev: drm device.
* @ipp_id: id of ipp driver.
* @dedicated: dedicated ipp device.
* @ops: source, destination operations.
* @event_workq: event work queue.
* @cmd: current command information.
* @cmd_list: list head for command information.
* @prop_list: property informations of current ipp driver.
* @check_property: check property about format, size, buffer.
* @reset: reset ipp block.
* @start: ipp each device start.
* @stop: ipp each device stop.
* @sched_event: work schedule handler.
*/
struct exynos_drm_ippdrv {
struct list_head drv_list;
struct device *parent_dev;
struct device *dev;
struct drm_device *drm_dev;
u32 ipp_id;
bool dedicated;
struct exynos_drm_ipp_ops *ops[EXYNOS_DRM_OPS_MAX];
struct workqueue_struct *event_workq;
struct drm_exynos_ipp_cmd_node *cmd;
struct list_head cmd_list;
struct drm_exynos_ipp_prop_list *prop_list;
int (*check_property)(struct device *dev,
struct drm_exynos_ipp_property *property);
int (*reset)(struct device *dev);
int (*start)(struct device *dev, enum drm_exynos_ipp_cmd cmd);
void (*stop)(struct device *dev, enum drm_exynos_ipp_cmd cmd);
void (*sched_event)(struct work_struct *work);
};
#ifdef CONFIG_DRM_EXYNOS_IPP
extern int exynos_drm_ippdrv_register(struct exynos_drm_ippdrv *ippdrv);
extern int exynos_drm_ippdrv_unregister(struct exynos_drm_ippdrv *ippdrv);
extern int exynos_drm_ipp_get_property(struct drm_device *drm_dev, void *data,
struct drm_file *file);
extern int exynos_drm_ipp_set_property(struct drm_device *drm_dev, void *data,
struct drm_file *file);
extern int exynos_drm_ipp_queue_buf(struct drm_device *drm_dev, void *data,
struct drm_file *file);
extern int exynos_drm_ipp_cmd_ctrl(struct drm_device *drm_dev, void *data,
struct drm_file *file);
extern int exynos_drm_ippnb_register(struct notifier_block *nb);
extern int exynos_drm_ippnb_unregister(struct notifier_block *nb);
extern int exynos_drm_ippnb_send_event(unsigned long val, void *v);
extern void ipp_sched_cmd(struct work_struct *work);
extern void ipp_sched_event(struct work_struct *work);
#else
static inline int exynos_drm_ippdrv_register(struct exynos_drm_ippdrv *ippdrv)
{
return -ENODEV;
}
static inline int exynos_drm_ippdrv_unregister(struct exynos_drm_ippdrv *ippdrv)
{
return -ENODEV;
}
static inline int exynos_drm_ipp_get_property(struct drm_device *drm_dev,
void *data,
struct drm_file *file_priv)
{
return -ENOTTY;
}
static inline int exynos_drm_ipp_set_property(struct drm_device *drm_dev,
void *data,
struct drm_file *file_priv)
{
return -ENOTTY;
}
static inline int exynos_drm_ipp_queue_buf(struct drm_device *drm_dev,
void *data,
struct drm_file *file)
{
return -ENOTTY;
}
static inline int exynos_drm_ipp_cmd_ctrl(struct drm_device *drm_dev,
void *data,
struct drm_file *file)
{
return -ENOTTY;
}
static inline int exynos_drm_ippnb_register(struct notifier_block *nb)
{
return -ENODEV;
}
static inline int exynos_drm_ippnb_unregister(struct notifier_block *nb)
{
return -ENODEV;
}
static inline int exynos_drm_ippnb_send_event(unsigned long val, void *v)
{
return -ENOTTY;
}
#endif
#endif /* _EXYNOS_DRM_IPP_H_ */

190
include/uapi/drm/exynos_drm.h
View File

@ -163,6 +163,170 @@ struct drm_exynos_g2d_exec {
__u64 async;
};
enum drm_exynos_ops_id {
EXYNOS_DRM_OPS_SRC,
EXYNOS_DRM_OPS_DST,
EXYNOS_DRM_OPS_MAX,
};
struct drm_exynos_sz {
__u32 hsize;
__u32 vsize;
};
struct drm_exynos_pos {
__u32 x;
__u32 y;
__u32 w;
__u32 h;
};
enum drm_exynos_flip {
EXYNOS_DRM_FLIP_NONE = (0 << 0),
EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
};
enum drm_exynos_degree {
EXYNOS_DRM_DEGREE_0,
EXYNOS_DRM_DEGREE_90,
EXYNOS_DRM_DEGREE_180,
EXYNOS_DRM_DEGREE_270,
};
enum drm_exynos_planer {
EXYNOS_DRM_PLANAR_Y,
EXYNOS_DRM_PLANAR_CB,
EXYNOS_DRM_PLANAR_CR,
EXYNOS_DRM_PLANAR_MAX,
};
/**
* A structure for ipp supported property list.
*
* @version: version of this structure.
* @ipp_id: id of ipp driver.
* @count: count of ipp driver.
* @writeback: flag of writeback supporting.
* @flip: flag of flip supporting.
* @degree: flag of degree information.
* @csc: flag of csc supporting.
* @crop: flag of crop supporting.
* @scale: flag of scale supporting.
* @refresh_min: min hz of refresh.
* @refresh_max: max hz of refresh.
* @crop_min: crop min resolution.
* @crop_max: crop max resolution.
* @scale_min: scale min resolution.
* @scale_max: scale max resolution.
*/
struct drm_exynos_ipp_prop_list {
__u32 version;
__u32 ipp_id;
__u32 count;
__u32 writeback;
__u32 flip;
__u32 degree;
__u32 csc;
__u32 crop;
__u32 scale;
__u32 refresh_min;
__u32 refresh_max;
__u32 reserved;
struct drm_exynos_sz crop_min;
struct drm_exynos_sz crop_max;
struct drm_exynos_sz scale_min;
struct drm_exynos_sz scale_max;
};
/**
* A structure for ipp config.
*
* @ops_id: property of operation directions.
* @flip: property of mirror, flip.
* @degree: property of rotation degree.
* @fmt: property of image format.
* @sz: property of image size.
* @pos: property of image position(src-cropped,dst-scaler).
*/
struct drm_exynos_ipp_config {
enum drm_exynos_ops_id ops_id;
enum drm_exynos_flip flip;
enum drm_exynos_degree degree;
__u32 fmt;
struct drm_exynos_sz sz;
struct drm_exynos_pos pos;
};
enum drm_exynos_ipp_cmd {
IPP_CMD_NONE,
IPP_CMD_M2M,
IPP_CMD_WB,
IPP_CMD_OUTPUT,
IPP_CMD_MAX,
};
/**
* A structure for ipp property.
*
* @config: source, destination config.
* @cmd: definition of command.
* @ipp_id: id of ipp driver.
* @prop_id: id of property.
* @refresh_rate: refresh rate.
*/
struct drm_exynos_ipp_property {
struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
enum drm_exynos_ipp_cmd cmd;
__u32 ipp_id;
__u32 prop_id;
__u32 refresh_rate;
};
enum drm_exynos_ipp_buf_type {
IPP_BUF_ENQUEUE,
IPP_BUF_DEQUEUE,
};
/**
* A structure for ipp buffer operations.
*
* @ops_id: operation directions.
* @buf_type: definition of buffer.
* @prop_id: id of property.
* @buf_id: id of buffer.
* @handle: Y, Cb, Cr each planar handle.
* @user_data: user data.
*/
struct drm_exynos_ipp_queue_buf {
enum drm_exynos_ops_id ops_id;
enum drm_exynos_ipp_buf_type buf_type;
__u32 prop_id;
__u32 buf_id;
__u32 handle[EXYNOS_DRM_PLANAR_MAX];
__u32 reserved;
__u64 user_data;
};
enum drm_exynos_ipp_ctrl {
IPP_CTRL_PLAY,
IPP_CTRL_STOP,
IPP_CTRL_PAUSE,
IPP_CTRL_RESUME,
IPP_CTRL_MAX,
};
/**
* A structure for ipp start/stop operations.
*
* @prop_id: id of property.
* @ctrl: definition of control.
*/
struct drm_exynos_ipp_cmd_ctrl {
__u32 prop_id;
enum drm_exynos_ipp_ctrl ctrl;
};
#define DRM_EXYNOS_GEM_CREATE 0x00
#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
#define DRM_EXYNOS_GEM_MMAP 0x02
@ -175,6 +339,12 @@ struct drm_exynos_g2d_exec {
#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
#define DRM_EXYNOS_G2D_EXEC 0x22
/* IPP - Image Post Processing */
#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
@ -197,8 +367,18 @@ struct drm_exynos_g2d_exec {
#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
/* EXYNOS specific events */
#define DRM_EXYNOS_G2D_EVENT 0x80000000
#define DRM_EXYNOS_IPP_EVENT 0x80000001
struct drm_exynos_g2d_event {
struct drm_event base;
@ -209,4 +389,14 @@ struct drm_exynos_g2d_event {
__u32 reserved;
};
struct drm_exynos_ipp_event {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 prop_id;
__u32 reserved;
__u32 buf_id[EXYNOS_DRM_OPS_MAX];
};
#endif /* _UAPI_EXYNOS_DRM_H_ */