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mtd: spi-nor: cadence-quadspi: add a delay in write sequence
commit 61dc8493ba
upstream
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.
[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
6442c97b5d
commit
cb47222af1
1 changed files with 26 additions and 1 deletions
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@ -38,6 +38,9 @@
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#define CQSPI_NAME "cadence-qspi"
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#define CQSPI_MAX_CHIPSELECT 16
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/* Quirks */
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#define CQSPI_NEEDS_WR_DELAY BIT(0)
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struct cqspi_st;
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struct cqspi_flash_pdata {
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@ -76,6 +79,7 @@ struct cqspi_st {
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u32 fifo_depth;
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u32 fifo_width;
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u32 trigger_address;
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u32 wr_delay;
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struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
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};
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@ -623,6 +627,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
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reinit_completion(&cqspi->transfer_complete);
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writel(CQSPI_REG_INDIRECTWR_START_MASK,
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reg_base + CQSPI_REG_INDIRECTWR);
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/*
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* As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
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* Controller programming sequence, couple of cycles of
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* QSPI_REF_CLK delay is required for the above bit to
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* be internally synchronized by the QSPI module. Provide 5
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* cycles of delay.
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*/
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if (cqspi->wr_delay)
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ndelay(cqspi->wr_delay);
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while (remaining > 0) {
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size_t write_words, mod_bytes;
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@ -1184,6 +1197,7 @@ static int cqspi_probe(struct platform_device *pdev)
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struct cqspi_st *cqspi;
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struct resource *res;
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struct resource *res_ahb;
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unsigned long data;
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int ret;
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int irq;
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@ -1241,6 +1255,10 @@ static int cqspi_probe(struct platform_device *pdev)
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}
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cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
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data = (unsigned long)of_device_get_match_data(dev);
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if (data & CQSPI_NEEDS_WR_DELAY)
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cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
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cqspi->master_ref_clk_hz);
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ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
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pdev->name, cqspi);
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@ -1312,7 +1330,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
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#endif
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static const struct of_device_id cqspi_dt_ids[] = {
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{.compatible = "cdns,qspi-nor",},
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{
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.compatible = "cdns,qspi-nor",
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.data = (void *)0,
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},
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{
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.compatible = "ti,k2g-qspi",
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.data = (void *)CQSPI_NEEDS_WR_DELAY,
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},
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{ /* end of table */ }
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};
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