Merge branch 'x86/apic' into x86/platform
Reason: Devicetree based ioapic setup depends on the apic changes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
commit
cb4cfd568c
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@ -811,7 +811,7 @@ config X86_LOCAL_APIC
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config X86_IO_APIC
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def_bool y
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depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC
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depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC
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config X86_VISWS_APIC
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def_bool y
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@ -426,4 +426,16 @@ struct local_apic {
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#else
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#define BAD_APICID 0xFFFFu
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#endif
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enum ioapic_irq_destination_types {
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dest_Fixed = 0,
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dest_LowestPrio = 1,
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dest_SMI = 2,
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dest__reserved_1 = 3,
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dest_NMI = 4,
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dest_INIT = 5,
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dest__reserved_2 = 6,
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dest_ExtINT = 7
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};
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#endif /* _ASM_X86_APICDEF_H */
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@ -63,17 +63,6 @@ union IO_APIC_reg_03 {
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} __attribute__ ((packed)) bits;
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};
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enum ioapic_irq_destination_types {
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dest_Fixed = 0,
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dest_LowestPrio = 1,
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dest_SMI = 2,
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dest__reserved_1 = 3,
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dest_NMI = 4,
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dest_INIT = 5,
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dest__reserved_2 = 6,
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dest_ExtINT = 7
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};
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struct IO_APIC_route_entry {
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__u32 vector : 8,
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delivery_mode : 3, /* 000: FIXED
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@ -106,6 +95,10 @@ struct IR_IO_APIC_route_entry {
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index : 15;
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} __attribute__ ((packed));
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#define IOAPIC_AUTO -1
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#define IOAPIC_EDGE 0
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#define IOAPIC_LEVEL 1
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#ifdef CONFIG_X86_IO_APIC
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/*
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@ -150,11 +143,6 @@ extern int timer_through_8259;
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#define io_apic_assign_pci_irqs \
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(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
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extern u8 io_apic_unique_id(u8 id);
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extern int io_apic_get_unique_id(int ioapic, int apic_id);
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extern int io_apic_get_version(int ioapic);
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extern int io_apic_get_redir_entries(int ioapic);
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struct io_apic_irq_attr;
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extern int io_apic_set_pci_routing(struct device *dev, int irq,
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struct io_apic_irq_attr *irq_attr);
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@ -162,6 +150,8 @@ void setup_IO_APIC_irq_extra(u32 gsi);
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extern void ioapic_and_gsi_init(void);
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extern void ioapic_insert_resources(void);
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int io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr);
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extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
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extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
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extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
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@ -186,6 +176,8 @@ extern void __init pre_init_apic_IRQ0(void);
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extern void mp_save_irq(struct mpc_intsrc *m);
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extern void disable_ioapic_support(void);
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#else /* !CONFIG_X86_IO_APIC */
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#define io_apic_assign_pci_irqs 0
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@ -199,6 +191,26 @@ static inline int mp_find_ioapic(u32 gsi) { return 0; }
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struct io_apic_irq_attr;
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static inline int io_apic_set_pci_routing(struct device *dev, int irq,
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struct io_apic_irq_attr *irq_attr) { return 0; }
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static inline struct IO_APIC_route_entry **alloc_ioapic_entries(void)
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{
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return NULL;
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}
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static inline void free_ioapic_entries(struct IO_APIC_route_entry **ent) { }
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static inline int save_IO_APIC_setup(struct IO_APIC_route_entry **ent)
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{
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return -ENOMEM;
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}
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static inline void mask_IO_APIC_setup(struct IO_APIC_route_entry **ent) { }
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static inline int restore_IO_APIC_setup(struct IO_APIC_route_entry **ent)
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{
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return -ENOMEM;
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}
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static inline void mp_save_irq(struct mpc_intsrc *m) { };
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static inline void disable_ioapic_support(void) { }
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#endif
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#endif /* _ASM_X86_IO_APIC_H */
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@ -43,6 +43,7 @@
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/desc.h>
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#include <asm/hpet.h>
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#include <asm/idle.h>
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@ -1209,7 +1210,7 @@ void __cpuinit setup_local_APIC(void)
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rdtscll(tsc);
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if (disable_apic) {
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arch_disable_smp_support();
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disable_ioapic_support();
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return;
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}
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@ -1448,7 +1449,7 @@ int __init enable_IR(void)
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void __init enable_IR_x2apic(void)
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{
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unsigned long flags;
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struct IO_APIC_route_entry **ioapic_entries = NULL;
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struct IO_APIC_route_entry **ioapic_entries;
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int ret, x2apic_enabled = 0;
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int dmar_table_init_ret;
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@ -108,7 +108,10 @@ DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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int skip_ioapic_setup;
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void arch_disable_smp_support(void)
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/**
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* disable_ioapic_support() - disables ioapic support at runtime
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*/
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void disable_ioapic_support(void)
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{
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#ifdef CONFIG_PCI
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noioapicquirk = 1;
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@ -120,11 +123,14 @@ void arch_disable_smp_support(void)
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static int __init parse_noapic(char *str)
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{
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/* disable IO-APIC */
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arch_disable_smp_support();
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disable_ioapic_support();
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return 0;
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}
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early_param("noapic", parse_noapic);
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static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
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struct io_apic_irq_attr *attr);
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/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
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void mp_save_irq(struct mpc_intsrc *m)
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{
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@ -818,7 +824,7 @@ static int EISA_ELCR(unsigned int irq)
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#define default_MCA_trigger(idx) (1)
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#define default_MCA_polarity(idx) default_ISA_polarity(idx)
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static int MPBIOS_polarity(int idx)
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static int irq_polarity(int idx)
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{
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int bus = mp_irqs[idx].srcbus;
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int polarity;
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@ -860,7 +866,7 @@ static int MPBIOS_polarity(int idx)
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return polarity;
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}
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static int MPBIOS_trigger(int idx)
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static int irq_trigger(int idx)
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{
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int bus = mp_irqs[idx].srcbus;
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int trigger;
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@ -932,16 +938,6 @@ static int MPBIOS_trigger(int idx)
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return trigger;
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}
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static inline int irq_polarity(int idx)
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{
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return MPBIOS_polarity(idx);
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}
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static inline int irq_trigger(int idx)
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{
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return MPBIOS_trigger(idx);
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}
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static int pin_2_irq(int idx, int apic, int pin)
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{
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int irq;
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@ -1220,10 +1216,6 @@ void __setup_vector_irq(int cpu)
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static struct irq_chip ioapic_chip;
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static struct irq_chip ir_ioapic_chip;
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#define IOAPIC_AUTO -1
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#define IOAPIC_EDGE 0
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#define IOAPIC_LEVEL 1
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#ifdef CONFIG_X86_32
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static inline int IO_APIC_irq_trigger(int irq)
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{
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@ -1385,33 +1377,26 @@ static struct {
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DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
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} mp_ioapic_routing[MAX_IO_APICS];
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static void __init setup_IO_APIC_irqs(void)
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static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
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{
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int apic_id, pin, idx, irq, notcon = 0;
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int node = cpu_to_node(0);
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struct irq_cfg *cfg;
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if (idx != -1)
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return false;
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apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
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apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
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mp_ioapics[apic_id].apicid, pin);
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return true;
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}
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static void __init __io_apic_setup_irqs(unsigned int apic_id)
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{
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int idx, node = cpu_to_node(0);
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struct io_apic_irq_attr attr;
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unsigned int pin, irq;
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for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
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for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
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idx = find_irq_entry(apic_id, pin, mp_INT);
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if (idx == -1) {
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if (!notcon) {
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notcon = 1;
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apic_printk(APIC_VERBOSE,
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KERN_DEBUG " %d-%d",
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mp_ioapics[apic_id].apicid, pin);
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} else
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apic_printk(APIC_VERBOSE, " %d-%d",
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mp_ioapics[apic_id].apicid, pin);
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if (io_apic_pin_not_connected(idx, apic_id, pin))
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continue;
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}
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if (notcon) {
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apic_printk(APIC_VERBOSE,
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" (apicid-pin) not connected\n");
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notcon = 0;
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}
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irq = pin_2_irq(idx, apic_id, pin);
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@ -1423,25 +1408,24 @@ static void __init setup_IO_APIC_irqs(void)
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* installed and if it returns 1:
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*/
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if (apic->multi_timer_check &&
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apic->multi_timer_check(apic_id, irq))
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apic->multi_timer_check(apic_id, irq))
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continue;
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cfg = alloc_irq_and_cfg_at(irq, node);
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if (!cfg)
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continue;
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set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
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irq_polarity(idx));
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add_pin_to_irq_node(cfg, node, apic_id, pin);
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/*
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* don't mark it in pin_programmed, so later acpi could
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* set it correctly when irq < 16
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*/
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setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
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irq_polarity(idx));
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io_apic_setup_irq_pin(irq, node, &attr);
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}
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}
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if (notcon)
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apic_printk(APIC_VERBOSE,
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" (apicid-pin) not connected\n");
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static void __init setup_IO_APIC_irqs(void)
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{
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unsigned int apic_id;
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apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
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for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
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__io_apic_setup_irqs(apic_id);
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}
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/*
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@ -1452,7 +1436,7 @@ static void __init setup_IO_APIC_irqs(void)
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void setup_IO_APIC_irq_extra(u32 gsi)
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{
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int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
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struct irq_cfg *cfg;
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struct io_apic_irq_attr attr;
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/*
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* Convert 'gsi' to 'ioapic.pin'.
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@ -1472,21 +1456,10 @@ void setup_IO_APIC_irq_extra(u32 gsi)
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if (apic_id == 0 || irq < NR_IRQS_LEGACY)
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return;
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cfg = alloc_irq_and_cfg_at(irq, node);
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if (!cfg)
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return;
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set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
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irq_polarity(idx));
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add_pin_to_irq_node(cfg, node, apic_id, pin);
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if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
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pr_debug("Pin %d-%d already programmed\n",
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mp_ioapics[apic_id].apicid, pin);
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return;
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}
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set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
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setup_ioapic_irq(apic_id, pin, irq, cfg,
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irq_trigger(idx), irq_polarity(idx));
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io_apic_setup_irq_pin_once(irq, node, &attr);
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}
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/*
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@ -3605,7 +3578,40 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
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}
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#endif /* CONFIG_HT_IRQ */
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int __init io_apic_get_redir_entries (int ioapic)
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int
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io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
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{
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struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
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int ret;
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if (!cfg)
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return -EINVAL;
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ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
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if (!ret)
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setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
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attr->trigger, attr->polarity);
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return ret;
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}
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static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
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struct io_apic_irq_attr *attr)
|
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{
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unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
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int ret;
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/* Avoid redundant programming */
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if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
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pr_debug("Pin %d-%d already programmed\n",
|
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mp_ioapics[id].apicid, pin);
|
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return 0;
|
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}
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ret = io_apic_setup_irq_pin(irq, node, attr);
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if (!ret)
|
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set_bit(pin, mp_ioapic_routing[id].pin_programmed);
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return ret;
|
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}
|
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|
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static int __init io_apic_get_redir_entries(int ioapic)
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{
|
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union IO_APIC_reg_01 reg_01;
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unsigned long flags;
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|
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@ -3659,96 +3665,24 @@ int __init arch_probe_nr_irqs(void)
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}
|
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#endif
|
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|
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static int __io_apic_set_pci_routing(struct device *dev, int irq,
|
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struct io_apic_irq_attr *irq_attr)
|
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int io_apic_set_pci_routing(struct device *dev, int irq,
|
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struct io_apic_irq_attr *irq_attr)
|
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{
|
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struct irq_cfg *cfg;
|
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int node;
|
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int ioapic, pin;
|
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int trigger, polarity;
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|
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ioapic = irq_attr->ioapic;
|
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if (!IO_APIC_IRQ(irq)) {
|
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apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
|
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ioapic);
|
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irq_attr->ioapic);
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return -EINVAL;
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}
|
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|
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if (dev)
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node = dev_to_node(dev);
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else
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node = cpu_to_node(0);
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node = dev ? dev_to_node(dev) : cpu_to_node(0);
|
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|
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cfg = alloc_irq_and_cfg_at(irq, node);
|
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if (!cfg)
|
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return 0;
|
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|
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pin = irq_attr->ioapic_pin;
|
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trigger = irq_attr->trigger;
|
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polarity = irq_attr->polarity;
|
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|
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/*
|
||||
* IRQs < 16 are already in the irq_2_pin[] map
|
||||
*/
|
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if (irq >= legacy_pic->nr_legacy_irqs) {
|
||||
if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) {
|
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printk(KERN_INFO "can not add pin %d for irq %d\n",
|
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pin, irq);
|
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return 0;
|
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}
|
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}
|
||||
|
||||
setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
|
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|
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return 0;
|
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}
|
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|
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int io_apic_set_pci_routing(struct device *dev, int irq,
|
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struct io_apic_irq_attr *irq_attr)
|
||||
{
|
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int ioapic, pin;
|
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/*
|
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* Avoid pin reprogramming. PRTs typically include entries
|
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* with redundant pin->gsi mappings (but unique PCI devices);
|
||||
* we only program the IOAPIC on the first.
|
||||
*/
|
||||
ioapic = irq_attr->ioapic;
|
||||
pin = irq_attr->ioapic_pin;
|
||||
if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
|
||||
pr_debug("Pin %d-%d already programmed\n",
|
||||
mp_ioapics[ioapic].apicid, pin);
|
||||
return 0;
|
||||
}
|
||||
set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
|
||||
|
||||
return __io_apic_set_pci_routing(dev, irq, irq_attr);
|
||||
}
|
||||
|
||||
u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
#ifdef CONFIG_X86_32
|
||||
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
||||
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
|
||||
return io_apic_get_unique_id(nr_ioapics, id);
|
||||
else
|
||||
return id;
|
||||
#else
|
||||
int i;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
|
||||
bitmap_zero(used, 256);
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
struct mpc_ioapic *ia = &mp_ioapics[i];
|
||||
__set_bit(ia->apicid, used);
|
||||
}
|
||||
if (!test_bit(id, used))
|
||||
return id;
|
||||
return find_first_zero_bit(used, 256);
|
||||
#endif
|
||||
return io_apic_setup_irq_pin_once(irq, node, irq_attr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
||||
static int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
||||
{
|
||||
union IO_APIC_reg_00 reg_00;
|
||||
static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
|
||||
|
|
@ -3821,9 +3755,33 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
|||
|
||||
return apic_id;
|
||||
}
|
||||
|
||||
static u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
||||
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
|
||||
return io_apic_get_unique_id(nr_ioapics, id);
|
||||
else
|
||||
return id;
|
||||
}
|
||||
#else
|
||||
static u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
int i;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
|
||||
bitmap_zero(used, 256);
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
struct mpc_ioapic *ia = &mp_ioapics[i];
|
||||
__set_bit(ia->apicid, used);
|
||||
}
|
||||
if (!test_bit(id, used))
|
||||
return id;
|
||||
return find_first_zero_bit(used, 256);
|
||||
}
|
||||
#endif
|
||||
|
||||
int __init io_apic_get_version(int ioapic)
|
||||
static int __init io_apic_get_version(int ioapic)
|
||||
{
|
||||
union IO_APIC_reg_01 reg_01;
|
||||
unsigned long flags;
|
||||
|
|
@ -4026,7 +3984,7 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi)
|
|||
return gsi - mp_gsi_routing[ioapic].gsi_base;
|
||||
}
|
||||
|
||||
static int bad_ioapic(unsigned long address)
|
||||
static __init int bad_ioapic(unsigned long address)
|
||||
{
|
||||
if (nr_ioapics >= MAX_IO_APICS) {
|
||||
printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
|
||||
|
|
@ -4086,20 +4044,15 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
|
|||
/* Enable IOAPIC early just for system timer */
|
||||
void __init pre_init_apic_IRQ0(void)
|
||||
{
|
||||
struct irq_cfg *cfg;
|
||||
struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
|
||||
|
||||
printk(KERN_INFO "Early APIC setup for system timer0\n");
|
||||
#ifndef CONFIG_SMP
|
||||
physid_set_mask_of_physid(boot_cpu_physical_apicid,
|
||||
&phys_cpu_present_map);
|
||||
#endif
|
||||
/* Make sure the irq descriptor is set up */
|
||||
cfg = alloc_irq_and_cfg_at(0, 0);
|
||||
|
||||
setup_local_APIC();
|
||||
|
||||
add_pin_to_irq_node(cfg, 0, 0, 0);
|
||||
io_apic_setup_irq_pin(0, 0, &attr);
|
||||
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
|
||||
|
||||
setup_ioapic_irq(0, 0, 0, cfg, 0, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@
|
|||
#include <asm/mtrr.h>
|
||||
#include <asm/mwait.h>
|
||||
#include <asm/apic.h>
|
||||
#include <asm/io_apic.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/uv/uv.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
|
|
@ -945,6 +946,14 @@ int __cpuinit native_cpu_up(unsigned int cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* arch_disable_smp_support() - disables SMP support for x86 at runtime
|
||||
*/
|
||||
void arch_disable_smp_support(void)
|
||||
{
|
||||
disable_ioapic_support();
|
||||
}
|
||||
|
||||
/*
|
||||
* Fall back to non SMP mode after errors.
|
||||
*
|
||||
|
|
@ -1045,7 +1054,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
|
|||
"(tell your hw vendor)\n");
|
||||
}
|
||||
smpboot_clear_io_apic();
|
||||
arch_disable_smp_support();
|
||||
disable_ioapic_support();
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue