mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 02:50:43 +00:00
octeontx2-pf: Prepare for QOS offload
This patch moves rate limiting definitions to a common header file and adds csr definitions required for QOS code. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
6b4b2ded9c
commit
cb748a7eba
3 changed files with 43 additions and 20 deletions
|
@ -185,6 +185,21 @@ struct mbox {
|
|||
int up_num_msgs; /* mbox_up number of messages */
|
||||
};
|
||||
|
||||
/* Egress rate limiting definitions */
|
||||
#define MAX_BURST_EXPONENT 0x0FULL
|
||||
#define MAX_BURST_MANTISSA 0xFFULL
|
||||
#define MAX_BURST_SIZE 130816ULL
|
||||
#define MAX_RATE_DIVIDER_EXPONENT 12ULL
|
||||
#define MAX_RATE_EXPONENT 0x0FULL
|
||||
#define MAX_RATE_MANTISSA 0xFFULL
|
||||
|
||||
/* Bitfields in NIX_TLX_PIR register */
|
||||
#define TLX_RATE_MANTISSA GENMASK_ULL(8, 1)
|
||||
#define TLX_RATE_EXPONENT GENMASK_ULL(12, 9)
|
||||
#define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13)
|
||||
#define TLX_BURST_MANTISSA GENMASK_ULL(36, 29)
|
||||
#define TLX_BURST_EXPONENT GENMASK_ULL(40, 37)
|
||||
|
||||
struct otx2_hw {
|
||||
struct pci_dev *pdev;
|
||||
struct otx2_rss_info rss_info;
|
||||
|
@ -253,6 +268,7 @@ struct otx2_hw {
|
|||
#define CN10K_RPM 3
|
||||
#define CN10K_PTP_ONESTEP 4
|
||||
#define CN10K_HW_MACSEC 5
|
||||
#define QOS_CIR_PIR_SUPPORT 6
|
||||
unsigned long cap_flag;
|
||||
|
||||
#define LMT_LINE_SIZE 128
|
||||
|
@ -591,6 +607,7 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
|
|||
__set_bit(CN10K_LMTST, &hw->cap_flag);
|
||||
__set_bit(CN10K_RPM, &hw->cap_flag);
|
||||
__set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag);
|
||||
__set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag);
|
||||
}
|
||||
|
||||
if (is_dev_cn10kb(pfvf->pdev))
|
||||
|
@ -915,6 +932,17 @@ static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf)
|
|||
return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues;
|
||||
}
|
||||
|
||||
static inline u64 otx2_convert_rate(u64 rate)
|
||||
{
|
||||
u64 converted_rate;
|
||||
|
||||
/* Convert bytes per second to Mbps */
|
||||
converted_rate = rate * 8;
|
||||
converted_rate = max_t(u64, converted_rate / 1000000, 1);
|
||||
|
||||
return converted_rate;
|
||||
}
|
||||
|
||||
/* MSI-X APIs */
|
||||
void otx2_free_cints(struct otx2_nic *pfvf, int n);
|
||||
void otx2_set_cints_affinity(struct otx2_nic *pfvf);
|
||||
|
|
|
@ -145,12 +145,25 @@
|
|||
#define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16)
|
||||
#define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16)
|
||||
#define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16)
|
||||
#define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16)
|
||||
#define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16)
|
||||
#define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16)
|
||||
#define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16)
|
||||
#define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16)
|
||||
#define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16)
|
||||
#define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16)
|
||||
#define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16)
|
||||
#define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16)
|
||||
#define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16)
|
||||
#define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16)
|
||||
#define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16)
|
||||
#define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16)
|
||||
#define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16)
|
||||
#define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16)
|
||||
#define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16)
|
||||
#define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16)
|
||||
#define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16)
|
||||
#define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16)
|
||||
#define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16)
|
||||
#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3)
|
||||
|
||||
|
|
|
@ -20,24 +20,9 @@
|
|||
#include "cn10k.h"
|
||||
#include "otx2_common.h"
|
||||
|
||||
/* Egress rate limiting definitions */
|
||||
#define MAX_BURST_EXPONENT 0x0FULL
|
||||
#define MAX_BURST_MANTISSA 0xFFULL
|
||||
#define MAX_BURST_SIZE 130816ULL
|
||||
#define MAX_RATE_DIVIDER_EXPONENT 12ULL
|
||||
#define MAX_RATE_EXPONENT 0x0FULL
|
||||
#define MAX_RATE_MANTISSA 0xFFULL
|
||||
|
||||
#define CN10K_MAX_BURST_MANTISSA 0x7FFFULL
|
||||
#define CN10K_MAX_BURST_SIZE 8453888ULL
|
||||
|
||||
/* Bitfields in NIX_TLX_PIR register */
|
||||
#define TLX_RATE_MANTISSA GENMASK_ULL(8, 1)
|
||||
#define TLX_RATE_EXPONENT GENMASK_ULL(12, 9)
|
||||
#define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13)
|
||||
#define TLX_BURST_MANTISSA GENMASK_ULL(36, 29)
|
||||
#define TLX_BURST_EXPONENT GENMASK_ULL(40, 37)
|
||||
|
||||
#define CN10K_TLX_BURST_MANTISSA GENMASK_ULL(43, 29)
|
||||
#define CN10K_TLX_BURST_EXPONENT GENMASK_ULL(47, 44)
|
||||
|
||||
|
@ -264,7 +249,6 @@ static int otx2_tc_egress_matchall_install(struct otx2_nic *nic,
|
|||
struct netlink_ext_ack *extack = cls->common.extack;
|
||||
struct flow_action *actions = &cls->rule->action;
|
||||
struct flow_action_entry *entry;
|
||||
u64 rate;
|
||||
int err;
|
||||
|
||||
err = otx2_tc_validate_flow(nic, actions, extack);
|
||||
|
@ -288,10 +272,8 @@ static int otx2_tc_egress_matchall_install(struct otx2_nic *nic,
|
|||
NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
/* Convert bytes per second to Mbps */
|
||||
rate = entry->police.rate_bytes_ps * 8;
|
||||
rate = max_t(u64, rate / 1000000, 1);
|
||||
err = otx2_set_matchall_egress_rate(nic, entry->police.burst, rate);
|
||||
err = otx2_set_matchall_egress_rate(nic, entry->police.burst,
|
||||
otx2_convert_rate(entry->police.rate_bytes_ps));
|
||||
if (err)
|
||||
return err;
|
||||
nic->flags |= OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED;
|
||||
|
|
Loading…
Reference in a new issue