mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 02:50:43 +00:00
sh: Preparation for uncached jumps through PMB.
Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
325df7f204
commit
cbaa118ecf
14 changed files with 88 additions and 56 deletions
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@ -64,11 +64,11 @@ static void __init speculative_execution_init(void)
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* Generic first-level cache init
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*/
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#ifdef CONFIG_SUPERH32
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static void __init cache_init(void)
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static void __uses_jump_to_uncached cache_init(void)
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{
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unsigned long ccr, flags;
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jump_to_P2();
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jump_to_uncached();
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ccr = ctrl_inl(CCR);
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/*
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@ -145,7 +145,7 @@ static void __init cache_init(void)
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#endif
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ctrl_outl(flags, CCR);
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back_to_P1();
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back_to_cached();
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}
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#else
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#define cache_init() do { } while (0)
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@ -16,11 +16,11 @@
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#include <asm/cache.h>
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#include <asm/io.h>
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int __init detect_cpu_and_cache_system(void)
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int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
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{
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unsigned long addr0, addr1, data0, data1, data2, data3;
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jump_to_P2();
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jump_to_uncached();
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/*
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* Check if the entry shadows or not.
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* When shadowed, it's 128-entry system.
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@ -48,7 +48,7 @@ int __init detect_cpu_and_cache_system(void)
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ctrl_outl(data0&~SH_CACHE_VALID, addr0);
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ctrl_outl(data2&~SH_CACHE_VALID, addr1);
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back_to_P1();
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back_to_cached();
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.dcache.entry_shift = 4;
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@ -43,6 +43,15 @@ SECTIONS
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NOTES
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RO_DATA(PAGE_SIZE)
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/*
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* Code which must be executed uncached and the associated data
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*/
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. = ALIGN(PAGE_SIZE);
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__uncached_start = .;
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.uncached.text : { *(.uncached.text) }
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.uncached.data : { *(.uncached.data) }
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__uncached_end = .;
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. = ALIGN(THREAD_SIZE);
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.data : { /* Data */
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*(.data.init_task)
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@ -22,7 +22,8 @@ enum cache_type {
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CACHE_TYPE_UNIFIED,
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};
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static int cache_seq_show(struct seq_file *file, void *iter)
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static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file,
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void *iter)
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{
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unsigned int cache_type = (unsigned int)file->private;
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struct cache_info *cache;
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@ -34,11 +35,11 @@ static int cache_seq_show(struct seq_file *file, void *iter)
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* Go uncached immediately so we don't skew the results any
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* more than we already are..
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*/
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jump_to_P2();
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jump_to_uncached();
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ccr = ctrl_inl(CCR);
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if ((ccr & CCR_CACHE_ENABLE) == 0) {
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back_to_P1();
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back_to_cached();
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seq_printf(file, "disabled\n");
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return 0;
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@ -104,7 +105,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
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addrstart += cache->way_incr;
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}
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back_to_P1();
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back_to_cached();
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return 0;
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}
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@ -190,7 +190,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
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* .. which happens to be the same behavior as flush_icache_range().
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* So, we simply flush out a line.
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*/
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void flush_cache_sigtramp(unsigned long addr)
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void __uses_jump_to_uncached flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long v, index;
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unsigned long flags;
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@ -205,13 +205,13 @@ void flush_cache_sigtramp(unsigned long addr)
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(v & boot_cpu_data.icache.entry_mask);
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local_irq_save(flags);
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jump_to_P2();
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jump_to_uncached();
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for (i = 0; i < boot_cpu_data.icache.ways;
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i++, index += boot_cpu_data.icache.way_incr)
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ctrl_outl(0, index); /* Clear out Valid-bit */
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back_to_P1();
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back_to_cached();
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wmb();
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local_irq_restore(flags);
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}
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@ -256,12 +256,12 @@ void flush_dcache_page(struct page *page)
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}
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/* TODO: Selective icache invalidation through IC address array.. */
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static inline void flush_icache_all(void)
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static inline void __uses_jump_to_uncached flush_icache_all(void)
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{
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unsigned long flags, ccr;
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local_irq_save(flags);
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jump_to_P2();
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jump_to_uncached();
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/* Flush I-cache */
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ccr = ctrl_inl(CCR);
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@ -269,11 +269,11 @@ static inline void flush_icache_all(void)
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ctrl_outl(ccr, CCR);
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/*
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* back_to_P1() will take care of the barrier for us, don't add
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* back_to_cached() will take care of the barrier for us, don't add
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* another one!
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*/
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back_to_P1();
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back_to_cached();
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local_irq_restore(flags);
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}
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@ -71,7 +71,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
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/*
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* Writeback&Invalidate the D-cache of the page
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*/
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static void __flush_dcache_page(unsigned long phys)
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static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys)
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{
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unsigned long ways, waysize, addrstart;
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unsigned long flags;
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@ -92,7 +92,7 @@ static void __flush_dcache_page(unsigned long phys)
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* possible.
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*/
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local_irq_save(flags);
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jump_to_P2();
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jump_to_uncached();
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ways = current_cpu_data.dcache.ways;
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waysize = current_cpu_data.dcache.sets;
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@ -118,7 +118,7 @@ static void __flush_dcache_page(unsigned long phys)
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addrstart += current_cpu_data.dcache.way_incr;
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} while (--ways);
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back_to_P1();
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back_to_cached();
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local_irq_restore(flags);
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}
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@ -132,15 +132,15 @@ void flush_dcache_page(struct page *page)
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__flush_dcache_page(PHYSADDR(page_address(page)));
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}
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void flush_cache_all(void)
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void __uses_jump_to_uncached flush_cache_all(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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jump_to_P2();
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jump_to_uncached();
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cache_wback_all();
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back_to_P1();
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back_to_cached();
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local_irq_restore(flags);
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}
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@ -23,6 +23,7 @@
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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pgd_t swapper_pg_dir[PTRS_PER_PGD];
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unsigned long cached_to_uncached = 0;
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void show_mem(void)
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{
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@ -99,7 +100,8 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
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set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot));
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flush_tlb_one(get_asid(), addr);
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if (cached_to_uncached)
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flush_tlb_one(get_asid(), addr);
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}
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/*
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@ -164,6 +166,18 @@ void __init paging_init(void)
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}
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free_area_init_nodes(max_zone_pfns);
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/* Set up the uncached fixmap */
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set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start));
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#ifdef CONFIG_29BIT
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/*
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* Handle trivial transitions between cached and uncached
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* segments, making use of the 1:1 mapping relationship in
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* 512MB lowmem.
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*/
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cached_to_uncached = P2SEG - P1SEG;
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#endif
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}
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static struct kcore_list kcore_mem, kcore_vmalloc;
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@ -163,18 +163,18 @@ int __set_pmb_entry(unsigned long vpn, unsigned long ppn,
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return 0;
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}
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int set_pmb_entry(struct pmb_entry *pmbe)
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int __uses_jump_to_uncached set_pmb_entry(struct pmb_entry *pmbe)
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{
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int ret;
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jump_to_P2();
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jump_to_uncached();
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ret = __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, &pmbe->entry);
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back_to_P1();
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back_to_cached();
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return ret;
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}
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void clear_pmb_entry(struct pmb_entry *pmbe)
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void __uses_jump_to_uncached clear_pmb_entry(struct pmb_entry *pmbe)
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{
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unsigned int entry = pmbe->entry;
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unsigned long addr;
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entry >= NR_PMB_ENTRIES))
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return;
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jump_to_P2();
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jump_to_uncached();
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/* Clear V-bit */
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addr = mk_pmb_addr(entry);
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addr = mk_pmb_data(entry);
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ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr);
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back_to_P1();
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back_to_cached();
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clear_bit(entry, &pmb_map);
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}
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@ -302,7 +302,7 @@ static void pmb_cache_ctor(struct kmem_cache *cachep, void *pmb)
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pmbe->entry = PMB_NO_ENTRY;
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}
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static int __init pmb_init(void)
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static int __uses_jump_to_uncached pmb_init(void)
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{
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unsigned int nr_entries = ARRAY_SIZE(pmb_init_map);
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unsigned int entry, i;
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pmb_cache = kmem_cache_create("pmb", sizeof(struct pmb_entry), 0,
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SLAB_PANIC, pmb_cache_ctor);
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jump_to_P2();
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jump_to_uncached();
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/*
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* Ordering is important, P2 must be mapped in the PMB before we
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i |= MMUCR_TI;
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ctrl_outl(i, MMUCR);
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back_to_P1();
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back_to_cached();
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return 0;
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}
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@ -79,7 +79,8 @@ void update_mmu_cache(struct vm_area_struct * vma,
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local_irq_restore(flags);
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}
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
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unsigned long page)
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{
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unsigned long addr, data;
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*/
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addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
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data = page | asid; /* VALID bit is off */
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jump_to_P2();
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jump_to_uncached();
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ctrl_outl(data, addr);
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back_to_P1();
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back_to_cached();
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}
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@ -49,6 +49,7 @@ enum fixed_addresses {
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#define FIX_N_COLOURS 16
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FIX_CMAP_BEGIN,
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FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
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FIX_UNCACHED,
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#ifdef CONFIG_HIGHMEM
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FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
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FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
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@ -4,6 +4,7 @@
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#include <asm-generic/sections.h>
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extern long __machvec_start, __machvec_end;
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extern char __uncached_start, __uncached_end;
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extern char _ebss[];
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#endif /* __ASM_SH_SECTIONS_H */
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@ -144,6 +144,8 @@ extern unsigned int instruction_size(unsigned int insn);
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#define instruction_size(insn) (4)
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#endif
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extern unsigned long cached_to_uncached;
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/* XXX
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* disable hlt during certain critical i/o operations
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*/
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@ -58,29 +58,31 @@ do { \
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last = __last; \
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} while (0)
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#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
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/*
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* Jump to P2 area.
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* When handling TLB or caches, we need to do it from P2 area.
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* Jump to uncached area.
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* When handling TLB or caches, we need to do it from an uncached area.
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*/
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#define jump_to_P2() \
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"or %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy) \
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: "r" (0x20000000)); \
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#define jump_to_uncached() \
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do { \
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unsigned long __dummy; \
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\
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__asm__ __volatile__( \
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"mova 1f, %0\n\t" \
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"add %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1:" \
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: "=&z" (__dummy) \
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: "r" (cached_to_uncached)); \
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} while (0)
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/*
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* Back to P1 area.
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* Back to cached area.
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*/
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#define back_to_P1() \
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#define back_to_cached() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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@ -32,8 +32,9 @@ do { \
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&next->thread); \
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} while (0)
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/* No segmentation.. */
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#define jump_to_P2() do { } while (0)
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#define back_to_P1() do { } while (0)
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#define __uses_jump_to_uncached
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#define jump_to_uncached() do { } while (0)
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#define back_to_cached() do { } while (0)
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#endif /* __ASM_SH_SYSTEM_64_H */
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