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This converts all DaVinci SoCs except DM365 to use new clocksource 

driver. DM365 conversion is still under debug and will be part of a
 future pull request.
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Merge tag 'davinci-for-v5.4/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/soc

This converts all DaVinci SoCs except DM365 to use new clocksource
driver. DM365 conversion is still under debug and will be part of a
future pull request.

* tag 'davinci-for-v5.4/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: dm646x: Fix a typo in the comment
  ARM: davinci: dm646x: switch to using the clocksource driver
  ARM: davinci: dm644x: switch to using the clocksource driver
  ARM: davinci: dm355: switch to using the clocksource driver
  ARM: davinci: move timer definitions to davinci.h
  ARM: davinci: da830: switch to using the clocksource driver
  ARM: davinci: da850: switch to using the clocksource driver
  ARM: davinci: WARN_ON() if clk_get() fails
  ARM: davinci: enable the clocksource driver for DT mode

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-04 15:13:27 +02:00
parent 9e38081e5d 93eae12c9f
commit cc1770a65e
10 changed files with 95 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -514,6 +514,7 @@ config ARCH_DAVINCI
select ARCH_HAS_HOLES_MEMORYMODEL
select COMMON_CLK
select CPU_ARM926T
select DAVINCI_TIMER
select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP

45
arch/arm/mach-davinci/da830.c
View File

@ -21,7 +21,8 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h"
#include "mux.h"
@ -676,32 +677,17 @@ int __init da830_register_gpio(void)
return da8xx_register_gpio(&da830_gpio_platform_data);
}
static struct davinci_timer_instance da830_timer_instance[2] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
.cmp_off = DA830_CMP12_0,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
.cmp_off = DA830_CMP12_0,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1),
},
};
/*
* T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
* T0_TOP: Timer 0, top : Used by DSP
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
* Bottom half of timer0 is used both for clock even and clocksource.
* Top half is used by DSP.
*/
static struct davinci_timer_info da830_timer_info = {
.timers = da830_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_BOT,
static const struct davinci_timer_cfg da830_timer_cfg = {
.reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
},
.cmp_off = DA830_CMP12_0,
};
static const struct davinci_soc_info davinci_soc_info_da830 = {
@ -713,7 +699,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
.timer_info = &da830_timer_info,
.emac_pdata = &da8xx_emac_pdata,
};
@ -743,6 +728,7 @@ void __init da830_init_time(void)
{
void __iomem *pll;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
@ -751,8 +737,13 @@ void __init da830_init_time(void)
da830_pll_init(NULL, pll, NULL);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &da830_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource da830_psc0_resources[] = {

50
arch/arm/mach-davinci/da850.c
View File

@ -35,7 +35,8 @@
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/pm.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h"
#include "mux.h"
@ -333,38 +334,16 @@ static struct davinci_id da850_ids[] = {
},
};
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
},
{
.base = DA850_TIMER64P2_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
},
{
.base = DA850_TIMER64P3_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
},
};
/*
* T0_BOT: Timer 0, bottom : Used for clock_event
* T0_TOP: Timer 0, top : Used for clocksource
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
* Bottom half of timer 0 is used for clock_event, top half for
* clocksource.
*/
static struct davinci_timer_info da850_timer_info = {
.timers = da850_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg da850_timer_cfg = {
.reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
},
};
#ifdef CONFIG_CPU_FREQ
@ -635,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
.timer_info = &da850_timer_info,
.emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE,
.sram_len = SZ_128K,
@ -672,6 +650,7 @@ void __init da850_init_time(void)
void __iomem *pll0;
struct regmap *cfgchip;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
@ -681,8 +660,13 @@ void __init da850_init_time(void)
da850_pll0_init(NULL, pll0, cfgchip);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &da850_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource da850_pll1_resources[] = {

3
arch/arm/mach-davinci/davinci.h
View File

@ -60,6 +60,9 @@ void davinci_map_sysmod(void);
#define DAVINCI_GPIO_BASE 0x01C67000
int davinci_gpio_register(struct resource *res, int size, void *pdata);
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
/* DM355 base addresses */
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000

28
arch/arm/mach-davinci/dm355.c
View File

@ -30,7 +30,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -620,15 +621,15 @@ static struct davinci_id dm355_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm355_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm355_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm355_serial0_platform_data[] = {
@ -706,7 +707,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm355_pins,
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
.timer_info = &dm355_timer_info,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
};
@ -733,6 +733,7 @@ void __init dm355_init_time(void)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
@ -743,8 +744,13 @@ void __init dm355_init_time(void)
dm355_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm355_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm355_pll2_resources[] = {

4
arch/arm/mach-davinci/dm365.c
View File

@ -784,6 +784,10 @@ void __init dm365_init_time(void)
dm365_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
}

28
arch/arm/mach-davinci/dm644x.c
View File

@ -27,7 +27,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -561,15 +562,15 @@ static struct davinci_id dm644x_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm644x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm644x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
@ -647,7 +648,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
.timer_info = &dm644x_timer_info,
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
.sram_len = SZ_16K,
@ -669,6 +669,7 @@ void __init dm644x_init_time(void)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
@ -679,8 +680,13 @@ void __init dm644x_init_time(void)
dm644x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm644x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm644x_pll2_resources[] = {

30
arch/arm/mach-davinci/dm646x.c
View File

@ -1,5 +1,5 @@
/*
* TI DaVinci DM644x chip specific setup
* TI DaVinci DM646x chip specific setup
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
@ -28,7 +28,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -501,15 +502,15 @@ static struct davinci_id dm646x_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm646x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm646x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
@ -587,7 +588,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
.timer_info = &dm646x_timer_info,
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
.sram_len = SZ_32K,
@ -652,6 +652,7 @@ void __init dm646x_init_time(unsigned long ref_clk_rate,
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
@ -663,8 +664,13 @@ void __init dm646x_init_time(unsigned long ref_clk_rate,
dm646x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm646x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm646x_pll2_resources[] = {

2
arch/arm/mach-davinci/include/mach/time.h
View File

@ -11,9 +11,7 @@
#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
#define __ARCH_ARM_MACH_DAVINCI_TIME_H
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
enum {
T0_BOT,

14
arch/arm/mach-davinci/time.c
View File

@ -398,17 +398,3 @@ void __init davinci_timer_init(struct clk *timer_clk)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
}
static int __init of_davinci_timer_init(struct device_node *np)
{
struct clk *clk;
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
return PTR_ERR(clk);
davinci_timer_init(clk);
return 0;
}
TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_init);