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clk: qcom: Add support for RCG to register for DFS
Dynamic Frequency switch is a feature of clock controller by which request from peripherals allows automatic switching frequency of input clock without SW intervention. There are various performance levels associated with a root clock. When the input performance state changes, the source clocks and division ratios of the new performance state are loaded on to RCG via HW and the RCG switches to new clock frequency when the RCG is in DFS HW enabled mode. Register the root clock generators(RCG) to switch to use the dfs clock ops in the cases where DFS is enabled. The clk_round_rate() called by the clock consumer would invoke the dfs determine clock ops and would read the DFS performance level registers to identify all the frequencies supported and update the frequency table. The DFS clock consumers would maintain these frequency mapping and request the desired performance levels. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Rework registration logic to stop copying, change recalc_rate() to index directly into the table if possible and fallback to calculating on the fly with an assumed correct parent] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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2 changed files with 205 additions and 0 deletions
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@ -163,4 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
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extern const struct clk_ops clk_gfx3d_ops;
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extern const struct clk_ops clk_rcg2_shared_ops;
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struct clk_rcg_dfs_data {
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struct clk_rcg2 *rcg;
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struct clk_init_data *init;
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};
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#define DEFINE_RCG_DFS(r) \
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{ .rcg = &r##_src, .init = &r##_init }
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extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
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const struct clk_rcg_dfs_data *rcgs,
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size_t len);
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#endif
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@ -12,6 +12,7 @@
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/math64.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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@ -40,6 +41,14 @@
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#define N_REG 0xc
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#define D_REG 0x10
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/* Dynamic Frequency Scaling */
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#define MAX_PERF_LEVEL 8
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#define SE_CMD_DFSR_OFFSET 0x14
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#define SE_CMD_DFS_EN BIT(0)
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#define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
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#define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
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#define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
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enum freq_policy {
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FLOOR,
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CEIL,
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@ -929,3 +938,188 @@ const struct clk_ops clk_rcg2_shared_ops = {
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.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
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/* Common APIs to be used for DFS based RCGR */
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static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
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struct freq_tbl *f)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct clk_hw *p;
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unsigned long prate = 0;
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u32 val, mask, cfg, mode;
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int i, num_parents;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
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mask = BIT(rcg->hid_width) - 1;
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f->pre_div = 1;
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if (cfg & mask)
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f->pre_div = cfg & mask;
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cfg &= CFG_SRC_SEL_MASK;
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cfg >>= CFG_SRC_SEL_SHIFT;
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num_parents = clk_hw_get_num_parents(hw);
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for (i = 0; i < num_parents; i++) {
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if (cfg == rcg->parent_map[i].cfg) {
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f->src = rcg->parent_map[i].src;
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p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
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prate = clk_hw_get_rate(p);
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}
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}
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mode = cfg & CFG_MODE_MASK;
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mode >>= CFG_MODE_SHIFT;
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if (mode) {
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mask = BIT(rcg->mnd_width) - 1;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
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&val);
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val &= mask;
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f->m = val;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
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&val);
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val = ~val;
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val &= mask;
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val += f->m;
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f->n = val;
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}
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f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
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}
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static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
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{
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struct freq_tbl *freq_tbl;
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int i;
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freq_tbl = kcalloc(MAX_PERF_LEVEL, sizeof(*freq_tbl), GFP_KERNEL);
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if (!freq_tbl)
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return -ENOMEM;
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rcg->freq_tbl = freq_tbl;
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for (i = 0; i < MAX_PERF_LEVEL; i++)
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clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
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return 0;
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}
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static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int ret;
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if (!rcg->freq_tbl) {
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ret = clk_rcg2_dfs_populate_freq_table(rcg);
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if (ret) {
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pr_err("Failed to update DFS tables for %s\n",
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clk_hw_get_name(hw));
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return ret;
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}
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}
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return clk_rcg2_determine_rate(hw, req);
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}
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static unsigned long
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clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
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regmap_read(rcg->clkr.regmap,
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rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
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level &= GENMASK(4, 1);
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level >>= 1;
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if (rcg->freq_tbl)
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return rcg->freq_tbl[level].freq;
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/*
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* Assume that parent_rate is actually the parent because
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* we can't do any better at figuring it out when the table
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* hasn't been populated yet. We only populate the table
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* in determine_rate because we can't guarantee the parents
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* will be registered with the framework until then.
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*/
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
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&cfg);
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mask = BIT(rcg->hid_width) - 1;
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pre_div = 1;
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if (cfg & mask)
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pre_div = cfg & mask;
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mode = cfg & CFG_MODE_MASK;
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mode >>= CFG_MODE_SHIFT;
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if (mode) {
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mask = BIT(rcg->mnd_width) - 1;
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regmap_read(rcg->clkr.regmap,
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rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
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m &= mask;
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regmap_read(rcg->clkr.regmap,
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rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
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n = ~n;
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n &= mask;
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n += m;
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}
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return calc_rate(parent_rate, m, n, mode, pre_div);
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}
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static const struct clk_ops clk_rcg2_dfs_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.determine_rate = clk_rcg2_dfs_determine_rate,
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.recalc_rate = clk_rcg2_dfs_recalc_rate,
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};
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static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
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struct regmap *regmap)
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{
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struct clk_rcg2 *rcg = data->rcg;
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struct clk_init_data *init = data->init;
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u32 val;
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int ret;
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ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
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if (ret)
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return -EINVAL;
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if (!(val & SE_CMD_DFS_EN))
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return 0;
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/*
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* Rate changes with consumer writing a register in
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* their own I/O region
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*/
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init->flags |= CLK_GET_RATE_NOCACHE;
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init->ops = &clk_rcg2_dfs_ops;
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rcg->freq_tbl = NULL;
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pr_debug("DFS registered for clk %s\n", init->name);
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return 0;
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}
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int qcom_cc_register_rcg_dfs(struct regmap *regmap,
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const struct clk_rcg_dfs_data *rcgs, size_t len)
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{
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int i, ret;
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for (i = 0; i < len; i++) {
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ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
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if (ret) {
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const char *name = rcgs[i].init->name;
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pr_err("DFS register failed for clk %s\n", name);
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return ret;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
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