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MIPS R2 instruction hazard handling.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2 changed files with 17 additions and 0 deletions
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@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
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args.end = end;
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on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
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instruction_hazard();
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}
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/*
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@ -228,6 +228,22 @@ __asm__(
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#endif
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#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
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#define instruction_hazard() \
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do { \
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__label__ __next; \
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__asm__ __volatile__( \
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" jr.hb %0 \n" \
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: \
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: "r" (&&__next)); \
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__next: \
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; \
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} while (0)
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#else
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#define instruction_hazard() do { } while (0)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_HAZARDS_H */
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