mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
Revert "drm/i915: Add DSC support to MST path"
This reverts commit e1a84ba850
.
Part of a series where patches were modified while applying to resolve
conflicts, leading to further conflicts between drm-misc-next and
drm-intel-next, resulting in build failures in drm-tip. To be applied
again on a baseline with drm-misc-next and drm-intel-next in sync.
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
parent
5fd5cc73e4
commit
cc6b2ba275
3 changed files with 42 additions and 174 deletions
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@ -116,6 +116,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
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}
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static void intel_dp_unset_edid(struct intel_dp *intel_dp);
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static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
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/* Is link rate UHBR and thus 128b/132b? */
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bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
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@ -671,12 +672,11 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
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return 6144 * 8;
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}
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u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay,
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bool bigjoiner,
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u32 pipe_bpp,
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u32 timeslots)
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static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay,
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bool bigjoiner,
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u32 pipe_bpp)
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{
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u32 bits_per_pixel, max_bpp_small_joiner_ram;
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int i;
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@ -687,9 +687,8 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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* for SST -> TimeSlotsPerMTP is 1,
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* for MST -> TimeSlotsPerMTP has to be calculated
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*/
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bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
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bits_per_pixel = (link_clock * lane_count * 8) /
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intel_dp_mode_to_fec_clock(mode_clock);
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drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
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/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
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max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
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@ -738,9 +737,9 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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return bits_per_pixel << 4;
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}
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u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock, int mode_hdisplay,
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bool bigjoiner)
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static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock, int mode_hdisplay,
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bool bigjoiner)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 min_slice_count, i;
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@ -947,8 +946,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
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return MODE_OK;
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}
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bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
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int hdisplay, int clock)
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static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
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int hdisplay, int clock)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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@ -1035,7 +1034,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
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target_clock,
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mode->hdisplay,
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bigjoiner,
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pipe_bpp, 1) >> 4;
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pipe_bpp) >> 4;
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dsc_slice_count =
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intel_dp_dsc_get_slice_count(intel_dp,
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target_clock,
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@ -1340,7 +1339,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
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return -EINVAL;
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}
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int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
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static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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int i, num_bpc;
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@ -1440,11 +1439,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
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return drm_dsc_compute_rc_parameters(vdsc_cfg);
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}
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int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state,
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struct link_config_limits *limits,
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int timeslots)
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static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state,
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struct link_config_limits *limits)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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@ -1495,8 +1493,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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adjusted_mode->crtc_clock,
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adjusted_mode->crtc_hdisplay,
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pipe_config->bigjoiner_pipes,
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pipe_bpp,
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timeslots);
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pipe_bpp);
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dsc_dp_slice_count =
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intel_dp_dsc_get_slice_count(intel_dp,
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adjusted_mode->crtc_clock,
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@ -1508,13 +1505,27 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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return -EINVAL;
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}
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pipe_config->dsc.compressed_bpp = min_t(u16,
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dsc_max_output_bpp >> 4,
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pipe_config->pipe_bpp);
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dsc_max_output_bpp >> 4,
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pipe_config->pipe_bpp);
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pipe_config->dsc.slice_count = dsc_dp_slice_count;
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drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
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pipe_config->dsc.compressed_bpp,
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pipe_config->dsc.slice_count);
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}
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/* As of today we support DSC for only RGB */
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if (intel_dp->force_dsc_bpp) {
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if (intel_dp->force_dsc_bpp >= 8 &&
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intel_dp->force_dsc_bpp < pipe_bpp) {
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drm_dbg_kms(&dev_priv->drm,
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"DSC BPP forced to %d",
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intel_dp->force_dsc_bpp);
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pipe_config->dsc.compressed_bpp =
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intel_dp->force_dsc_bpp;
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} else {
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drm_dbg_kms(&dev_priv->drm,
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"Invalid DSC BPP %d",
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intel_dp->force_dsc_bpp);
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}
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}
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/*
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* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
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* is greater than the maximum Cdclock and if slice count is even
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@ -1522,13 +1533,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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*/
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if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
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pipe_config->bigjoiner_pipes) {
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if (pipe_config->dsc.slice_count > 1) {
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pipe_config->dsc.dsc_split = true;
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} else {
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if (pipe_config->dsc.slice_count < 2) {
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drm_dbg_kms(&dev_priv->drm,
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"Cannot split stream to use 2 VDSC instances\n");
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return -EINVAL;
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}
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pipe_config->dsc.dsc_split = true;
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}
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ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
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@ -1617,7 +1628,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
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str_yes_no(ret), str_yes_no(joiner_needs_dsc),
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str_yes_no(intel_dp->force_dsc_en));
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ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
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conn_state, &limits, 1);
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conn_state, &limits);
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if (ret < 0)
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return ret;
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}
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@ -56,11 +56,6 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
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int intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state);
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int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state,
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struct link_config_limits *limits,
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int timeslots);
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bool intel_dp_is_edp(struct intel_dp *intel_dp);
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bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
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bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
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@ -101,18 +96,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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unsigned int type);
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bool intel_digital_port_connected(struct intel_encoder *encoder);
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int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
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u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
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u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay,
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bool bigjoiner,
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u32 pipe_bpp,
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u32 timeslots);
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u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
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int mode_clock, int mode_hdisplay,
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bool bigjoiner);
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bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
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int hdisplay, int clock);
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static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
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{
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@ -139,63 +139,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
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return 0;
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}
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static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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struct link_config_limits *limits)
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{
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struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
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struct intel_dp *intel_dp = &intel_mst->primary->dp;
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struct intel_connector *connector =
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to_intel_connector(conn_state->connector);
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struct drm_i915_private *i915 = to_i915(connector->base.dev);
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->hw.adjusted_mode;
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bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
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DP_DPCD_QUIRK_CONSTANT_N);
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int slots = -EINVAL;
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int i, num_bpc;
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u8 dsc_bpc[3] = {0};
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int min_bpp, max_bpp;
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u8 dsc_max_bpc;
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/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
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if (DISPLAY_VER(i915) >= 12)
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dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
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else
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dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
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max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
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min_bpp = limits->min_bpp;
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num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
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dsc_bpc);
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for (i = 0; i < num_bpc; i++) {
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if (max_bpp >= dsc_bpc[i] * 3)
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if (min_bpp > dsc_bpc[i] * 3)
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min_bpp = dsc_bpc[i] * 3;
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}
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drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
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min_bpp, max_bpp);
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slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
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min_bpp, limits,
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conn_state, 2 * 3, true);
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if (slots < 0)
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return slots;
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intel_link_compute_m_n(crtc_state->pipe_bpp,
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crtc_state->lane_count,
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adjusted_mode->crtc_clock,
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crtc_state->port_clock,
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&crtc_state->dp_m_n,
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constant_n, crtc_state->fec_enable);
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crtc_state->dp_m_n.tu = slots;
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return 0;
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}
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static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
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conn_state, &limits);
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if (ret == -EDEADLK)
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return ret;
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/* enable compression if the mode doesn't fit available BW */
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drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
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if (ret || intel_dp->force_dsc_en) {
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/*
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* Try to get at least some timeslots and then see, if
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* we can fit there with DSC.
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*/
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drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
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ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
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conn_state, &limits);
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if (ret < 0)
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return ret;
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ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
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conn_state, &limits,
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pipe_config->dp_m_n.tu);
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}
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if (ret)
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return ret;
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@ -833,10 +753,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
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int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
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int max_rate, mode_rate, max_lanes, max_link_clock;
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int ret;
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bool dsc = false, bigjoiner = false;
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u16 dsc_max_output_bpp = 0;
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u8 dsc_slice_count = 0;
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int target_clock = mode->clock;
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if (drm_connector_is_unregistered(connector)) {
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*status = MODE_ERROR;
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return 0;
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}
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if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
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bigjoiner = true;
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max_dotclk *= 2;
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}
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if (DISPLAY_VER(dev_priv) >= 10 &&
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drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
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/*
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* TBD pass the connector BPC,
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* for now U8_MAX so that max BPC on that platform would be picked
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*/
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int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
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if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
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dsc_max_output_bpp =
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intel_dp_dsc_get_output_bpp(dev_priv,
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max_link_clock,
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max_lanes,
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target_clock,
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mode->hdisplay,
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bigjoiner,
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pipe_bpp, 1) >> 4;
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dsc_slice_count =
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intel_dp_dsc_get_slice_count(intel_dp,
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target_clock,
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mode->hdisplay,
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bigjoiner);
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}
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dsc = dsc_max_output_bpp && dsc_slice_count;
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}
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/*
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* Big joiner configuration needs DSC for TGL which is not true for
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* XE_LPD where uncompressed joiner is supported.
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*/
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if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
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return MODE_CLOCK_HIGH;
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if (mode_rate > max_rate && !dsc)
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return MODE_CLOCK_HIGH;
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*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
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return 0;
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}
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