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pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration

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Move drive strength and output impedance values to the SoC-specific
configuration data structure (struct rzg2l_hwcfg).  This allows
extending the drive strength support for RZ/G3S.  Along with this the DS
values were converted to uA for simple integration with RZ/G3S support.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-18-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2023-09-29 08:39:04 +03:00 committed by Geert Uytterhoeven
parent 35a3610e5a
commit cca38201b4
1 changed files with 31 additions and 11 deletions
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42
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View file

@ -133,13 +133,30 @@ struct rzg2l_register_offsets {
u16 sd_ch;
};
/**
* enum rzg2l_iolh_index - starting indices in IOLH specific arrays
* @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
* @RZG2L_IOLH_IDX_MAX: maximum index
*/
enum rzg2l_iolh_index {
RZG2L_IOLH_IDX_3V3 = 0,
RZG2L_IOLH_IDX_MAX = 4,
};
/* Maximum number of driver strength entries per power source. */
#define RZG2L_IOLH_MAX_DS_ENTRIES (4)
/**
* struct rzg2l_hwcfg - hardware configuration data structure
* @regs: hardware specific register offsets
* @iolh_groupa_ua: IOLH group A uA specific values
* @iolh_groupb_oi: IOLH group B output impedance specific values
* @func_base: base number for port function (see register PFC)
*/
struct rzg2l_hwcfg {
const struct rzg2l_register_offsets regs;
u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
u16 iolh_groupb_oi[4];
u8 func_base;
};
@ -177,9 +194,6 @@ struct rzg2l_pinctrl {
struct mutex mutex; /* serialize adding groups and functions */
};
static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
@ -604,7 +618,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
return -EINVAL;
index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
arg = iolh_groupa_mA[index];
arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
break;
}
@ -615,7 +629,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
return -EINVAL;
index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
arg = iolh_groupb_oi[index];
arg = hwcfg->iolh_groupb_oi[index];
break;
}
@ -703,11 +717,12 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IOLH_A))
return -EINVAL;
for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
if (arg == iolh_groupa_mA[index])
for (index = RZG2L_IOLH_IDX_3V3;
index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
break;
}
if (index >= ARRAY_SIZE(iolh_groupa_mA))
if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
return -EINVAL;
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
@ -721,11 +736,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IOLH_B))
return -EINVAL;
for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
if (arg == iolh_groupb_oi[index])
for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
if (arg == hwcfg->iolh_groupb_oi[index])
break;
}
if (index >= ARRAY_SIZE(iolh_groupb_oi))
if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
return -EINVAL;
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
@ -1563,6 +1578,11 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.pwpr = 0x3014,
.sd_ch = 0x3000,
},
.iolh_groupa_ua = {
/* 3v3 power source */
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
},
.iolh_groupb_oi = { 100, 66, 50, 33, },
};
static struct rzg2l_pinctrl_data r9a07g043_data = {