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wifi: rt2x00: rework MT7620 PA/LNA RF calibration
1. Move MT7620 PA/LNA calibration code to dedicated functions. 2. For external PA/LNA devices, restore RF and BBP registers before R-Calibration. 3. Do Rx DCOC calibration again before RXIQ calibration. 4. Add some missing LNA related registers' initialization. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Acked-by: Stanislaw Gruszka <stf_xl@wp.pl> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/TYAP286MB0315979F92DC563019B8F238BCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
This commit is contained in:
Shiji Yang
Kalle Valo
parent
a28533c6be
commit
cca74bed37
2 changed files with 130 additions and 52 deletions
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@ -4468,41 +4468,6 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
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rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
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usleep_range(1000, 1500);
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if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
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&rt2x00dev->cap_flags)) {
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reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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reg |= 0x00000101;
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rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
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reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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reg |= 0x00000101;
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rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
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rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
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0x36303636);
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
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0x6C6C6B6C);
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rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
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0x6C6C6B6C);
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}
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}
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bbp = rt2800_bbp_read(rt2x00dev, 4);
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@ -5612,16 +5577,6 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
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}
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}
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rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
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if (rt2x00_rt(rt2x00dev, RT6352)) {
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 75, 0x68);
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rt2800_bbp_write(rt2x00dev, 76, 0x4C);
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rt2800_bbp_write(rt2x00dev, 79, 0x1C);
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rt2800_bbp_write(rt2x00dev, 80, 0x0C);
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rt2800_bbp_write(rt2x00dev, 82, 0xB6);
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}
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}
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}
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EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
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@ -10345,6 +10300,128 @@ static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
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rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
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}
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static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
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{
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
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rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
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}
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
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}
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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}
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 75, 0x60);
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rt2800_bbp_write(rt2x00dev, 76, 0x44);
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rt2800_bbp_write(rt2x00dev, 79, 0x1c);
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rt2800_bbp_write(rt2x00dev, 80, 0x0c);
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rt2800_bbp_write(rt2x00dev, 82, 0xB6);
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}
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a);
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c);
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rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c);
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}
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}
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static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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if (rt2x00_has_cap_external_pa(rt2x00dev) ||
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rt2x00_has_cap_external_lna_bg(rt2x00dev))
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rt2800_restore_rf_bbp_rt6352(rt2x00dev);
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rt2800_r_calibration(rt2x00dev);
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rt2800_rf_self_txdc_cal(rt2x00dev);
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rt2800_rxdcoc_calibration(rt2x00dev);
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rt2800_bw_filter_calibration(rt2x00dev, true);
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rt2800_bw_filter_calibration(rt2x00dev, false);
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rt2800_loft_iq_calibration(rt2x00dev);
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/* missing DPD calibration for internal PA devices */
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rt2800_rxdcoc_calibration(rt2x00dev);
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rt2800_rxiq_calibration(rt2x00dev);
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if (!rt2x00_has_cap_external_pa(rt2x00dev) &&
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!rt2x00_has_cap_external_lna_bg(rt2x00dev))
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return;
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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reg |= 0x00000101;
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rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
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reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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reg |= 0x00000101;
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rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
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}
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
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}
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
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}
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if (rt2x00_has_cap_external_pa(rt2x00dev))
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rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
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if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 75, 0x68);
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rt2800_bbp_write(rt2x00dev, 76, 0x4c);
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rt2800_bbp_write(rt2x00dev, 79, 0x1c);
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rt2800_bbp_write(rt2x00dev, 80, 0x0c);
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rt2800_bbp_write(rt2x00dev, 82, 0xb6);
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}
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if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
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rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c);
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rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c);
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}
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}
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static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
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{
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/* Initialize RF central register to default value */
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@ -10609,13 +10686,8 @@ static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
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rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
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rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
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rt2800_r_calibration(rt2x00dev);
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rt2800_rf_self_txdc_cal(rt2x00dev);
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rt2800_rxdcoc_calibration(rt2x00dev);
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rt2800_bw_filter_calibration(rt2x00dev, true);
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rt2800_bw_filter_calibration(rt2x00dev, false);
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rt2800_loft_iq_calibration(rt2x00dev);
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rt2800_rxiq_calibration(rt2x00dev);
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/* Do calibration and init PA/LNA */
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rt2800_calibration_rt6352(rt2x00dev);
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}
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static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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@ -1262,6 +1262,12 @@ rt2x00_has_cap_external_lna_bg(struct rt2x00_dev *rt2x00dev)
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return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_BG);
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}
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static inline bool
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rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev)
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{
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return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0);
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}
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static inline bool
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rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
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{
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