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drm/amdgpu: Initialize compute sdma and memory from kgd
v2: add missing MTYPE_NONCACHED enum Signed-off-by: Ben Goz <ben.goz@amd.com> Acked-by: Oded Gabbay <oded.gabbay@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4 changed files with 123 additions and 0 deletions
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@ -552,4 +552,10 @@
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#define VCE_CMD_IB_AUTO 0x00000005
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#define VCE_CMD_SEMAPHORE 0x00000006
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/* valid for both DEFAULT_MTYPE and APE1_MTYPE */
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enum {
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MTYPE_CACHED = 0,
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MTYPE_NONCACHED = 3
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};
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#endif
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@ -2009,6 +2009,46 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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/**
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* gmc_v7_0_init_compute_vmid - gart enable
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*
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* @rdev: amdgpu_device pointer
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*
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* Initialize compute vmid sh_mem registers
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*
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*/
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#define DEFAULT_SH_MEM_BASES (0x6000)
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#define FIRST_COMPUTE_VMID (8)
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#define LAST_COMPUTE_VMID (16)
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static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
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{
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int i;
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uint32_t sh_mem_config;
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uint32_t sh_mem_bases;
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/*
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* Configure apertures:
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* LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
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* Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
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* GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
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*/
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sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
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sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
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sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
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mutex_lock(&adev->srbm_mutex);
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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cik_srbm_select(adev, 0, 0, 0, i);
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/* CP and shaders */
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WREG32(mmSH_MEM_CONFIG, sh_mem_config);
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WREG32(mmSH_MEM_APE1_BASE, 1);
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WREG32(mmSH_MEM_APE1_LIMIT, 0);
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WREG32(mmSH_MEM_BASES, sh_mem_bases);
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}
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cik_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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/**
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* gfx_v7_0_gpu_init - setup the 3D engine
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*
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@ -2230,6 +2270,8 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
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cik_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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gmc_v7_0_init_compute_vmid(adev);
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WREG32(mmSX_DEBUG_1, 0x20);
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WREG32(mmTA_CNTL_AUX, 0x00010000);
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@ -1894,6 +1894,51 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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/**
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* gmc_v8_0_init_compute_vmid - gart enable
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*
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* @rdev: amdgpu_device pointer
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*
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* Initialize compute vmid sh_mem registers
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*
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*/
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#define DEFAULT_SH_MEM_BASES (0x6000)
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#define FIRST_COMPUTE_VMID (8)
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#define LAST_COMPUTE_VMID (16)
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static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
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{
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int i;
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uint32_t sh_mem_config;
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uint32_t sh_mem_bases;
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/*
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* Configure apertures:
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* LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
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* Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
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* GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
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*/
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sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
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sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
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SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
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MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
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SH_MEM_CONFIG__PRIVATE_ATC_MASK;
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mutex_lock(&adev->srbm_mutex);
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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vi_srbm_select(adev, 0, 0, 0, i);
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/* CP and shaders */
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WREG32(mmSH_MEM_CONFIG, sh_mem_config);
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WREG32(mmSH_MEM_APE1_BASE, 1);
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WREG32(mmSH_MEM_APE1_LIMIT, 0);
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WREG32(mmSH_MEM_BASES, sh_mem_bases);
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}
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vi_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
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{
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u32 gb_addr_config;
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@ -2113,6 +2158,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
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vi_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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gmc_v8_0_init_compute_vmid(adev);
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mutex_lock(&adev->grbm_idx_mutex);
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/*
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* making sure that the following register writes will be broadcasted
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@ -438,6 +438,31 @@ static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
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/* XXX todo */
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}
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/**
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* sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
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*
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* @adev: amdgpu_device pointer
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* @enable: enable/disable the DMA MEs context switch.
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*
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* Halt or unhalt the async dma engines context switch (VI).
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*/
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static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
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{
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u32 f32_cntl;
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int i;
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for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
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f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
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if (enable)
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
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AUTO_CTXSW_ENABLE, 1);
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else
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
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AUTO_CTXSW_ENABLE, 0);
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WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
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}
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}
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/**
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* sdma_v3_0_enable - stop the async dma engines
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*
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@ -648,6 +673,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
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/* unhalt the MEs */
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sdma_v3_0_enable(adev, true);
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/* enable sdma ring preemption */
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sdma_v3_0_ctx_switch_enable(adev, true);
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/* start the gfx rings and rlc compute queues */
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r = sdma_v3_0_gfx_resume(adev);
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@ -1079,6 +1106,7 @@ static int sdma_v3_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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sdma_v3_0_ctx_switch_enable(adev, false);
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sdma_v3_0_enable(adev, false);
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return 0;
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