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gpio: mpc8xxx: Remove *read_reg and *write_reg from struct mpc8xxx_gpio_chip
*read_reg and *write_reg can be removed because at all the places to call them, we can just use gc->read_reg/gc->write_reg instead. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
fa4007ca06
commit
cd0d3f58a0
1 changed files with 21 additions and 27 deletions
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@ -37,9 +37,6 @@ struct mpc8xxx_gpio_chip {
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void __iomem *regs;
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raw_spinlock_t lock;
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unsigned long (*read_reg)(void __iomem *reg);
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void (*write_reg)(void __iomem *reg, unsigned long data);
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int (*direction_output)(struct gpio_chip *chip,
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unsigned offset, int value);
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@ -58,8 +55,8 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
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u32 out_mask, out_shadow;
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out_mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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val = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
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val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
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out_shadow = gc->bgpio_data & out_mask;
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return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
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@ -101,10 +98,11 @@ static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned int mask;
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mask = mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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& mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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@ -120,8 +118,8 @@ static void mpc8xxx_irq_unmask(struct irq_data *d)
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@ -135,8 +133,8 @@ static void mpc8xxx_irq_mask(struct irq_data *d)
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@ -147,8 +145,8 @@ static void mpc8xxx_irq_ack(struct irq_data *d)
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
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gc->pin2mask(gc, irqd_to_hwirq(d)));
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
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gc->pin2mask(gc, irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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@ -160,16 +158,16 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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| gc->pin2mask(gc, irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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mpc8xxx_gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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& ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -184,6 +182,7 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gc = &mpc8xxx_gc->gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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@ -201,8 +200,7 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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| (2 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -210,16 +208,14 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift))
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
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| (1 << shift));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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mpc8xxx_gc->write_reg(reg,
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(mpc8xxx_gc->read_reg(reg) & ~(3 << shift)));
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@ -332,8 +328,6 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
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}
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mpc8xxx_gc->read_reg = gc->read_reg;
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mpc8xxx_gc->write_reg = gc->write_reg;
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mpc8xxx_gc->direction_output = gc->direction_output;
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if (!devtype)
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@ -366,8 +360,8 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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return 0;
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/* ack and mask all irqs */
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
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mpc8xxx_gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
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irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
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mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
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