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drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP
Matter of taste. STEP matches the enums. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/cf2dccd1c9c7fdcf5de08ea10a9265292b45d8c7.1616764798.git.jani.nikula@intel.com
This commit is contained in:
parent
34b7e27b88
commit
cd0fcf5af7
7 changed files with 16 additions and 16 deletions
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@ -5333,7 +5333,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
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if (IS_ALDERLAKE_S(dev_priv) ||
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if (IS_ALDERLAKE_S(dev_priv) ||
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IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
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IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
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IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
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IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
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/* Wa_1409767108:tgl,dg1,adl-s */
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/* Wa_1409767108:tgl,dg1,adl-s */
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table = wa_1409767108_buddy_page_masks;
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table = wa_1409767108_buddy_page_masks;
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else
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else
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@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
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if (intel_dp->psr.psr2_sel_fetch_enabled) {
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if (intel_dp->psr.psr2_sel_fetch_enabled) {
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/* WA 1408330847 */
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/* WA 1408330847 */
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if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
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if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
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IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
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IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
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intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
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intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
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DIS_RAM_BYPASS_PSR2_MAN_TRACK,
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DIS_RAM_BYPASS_PSR2_MAN_TRACK,
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@ -1109,7 +1109,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
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/* WA 1408330847 */
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/* WA 1408330847 */
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if (intel_dp->psr.psr2_sel_fetch_enabled &&
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if (intel_dp->psr.psr2_sel_fetch_enabled &&
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(IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
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(IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
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IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
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IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
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intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
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intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
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DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
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DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
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@ -1858,7 +1858,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
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{
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{
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/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
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/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
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if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
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if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
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IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
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IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
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return false;
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return false;
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return plane_id < PLANE_SPRITE4;
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return plane_id < PLANE_SPRITE4;
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@ -1093,19 +1093,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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gen12_gt_workarounds_init(i915, wal);
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gen12_gt_workarounds_init(i915, wal);
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/* Wa_1409420604:tgl */
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/* Wa_1409420604:tgl */
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if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
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if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
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wa_write_or(wal,
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wa_write_or(wal,
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SUBSLICE_UNIT_LEVEL_CLKGATE2,
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SUBSLICE_UNIT_LEVEL_CLKGATE2,
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CPSSUNIT_CLKGATE_DIS);
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CPSSUNIT_CLKGATE_DIS);
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/* Wa_1607087056:tgl also know as BUG:1409180338 */
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/* Wa_1607087056:tgl also know as BUG:1409180338 */
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if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
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if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
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wa_write_or(wal,
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wa_write_or(wal,
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SLICE_UNIT_LEVEL_CLKGATE,
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SLICE_UNIT_LEVEL_CLKGATE,
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L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
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L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
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/* Wa_1408615072:tgl[a0] */
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/* Wa_1408615072:tgl[a0] */
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if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
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if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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VSUNIT_CLKGATE_DIS_TGL);
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VSUNIT_CLKGATE_DIS_TGL);
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}
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}
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@ -1583,7 +1583,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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struct drm_i915_private *i915 = engine->i915;
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struct drm_i915_private *i915 = engine->i915;
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if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
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if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
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IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
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IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
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/*
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/*
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* Wa_1607138336:tgl[a0],dg1[a0]
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* Wa_1607138336:tgl[a0],dg1[a0]
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* Wa_1607063988:tgl[a0],dg1[a0]
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* Wa_1607063988:tgl[a0],dg1[a0]
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@ -1593,7 +1593,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
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GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
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}
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}
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if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
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if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
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/*
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/*
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* Wa_1606679103:tgl
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* Wa_1606679103:tgl
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* (see also Wa_1606682166:icl)
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* (see also Wa_1606682166:icl)
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@ -1502,15 +1502,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_JSL_EHL_REVID(p, since, until) \
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#define IS_JSL_EHL_REVID(p, since, until) \
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(IS_JSL_EHL(p) && IS_REVID(p, since, until))
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(IS_JSL_EHL(p) && IS_REVID(p, since, until))
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#define IS_TGL_DISP_STEPPING(__i915, since, until) \
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#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
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(IS_TIGERLAKE(__i915) && \
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(IS_TIGERLAKE(__i915) && \
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IS_DISPLAY_STEP(__i915, since, until))
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IS_DISPLAY_STEP(__i915, since, until))
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#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \
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#define IS_TGL_UY_GT_STEP(__i915, since, until) \
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((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
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((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
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IS_GT_STEP(__i915, since, until))
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IS_GT_STEP(__i915, since, until))
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#define IS_TGL_GT_STEPPING(__i915, since, until) \
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#define IS_TGL_GT_STEP(__i915, since, until) \
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(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
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(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
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IS_GT_STEP(__i915, since, until))
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IS_GT_STEP(__i915, since, until))
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@ -1527,11 +1527,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_DG1_REVID(p, since, until) \
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#define IS_DG1_REVID(p, since, until) \
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(IS_DG1(p) && IS_REVID(p, since, until))
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(IS_DG1(p) && IS_REVID(p, since, until))
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#define IS_ADLS_DISP_STEPPING(__i915, since, until) \
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#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
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(IS_ALDERLAKE_S(__i915) && \
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(IS_ALDERLAKE_S(__i915) && \
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IS_DISPLAY_STEP(__i915, since, until))
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IS_DISPLAY_STEP(__i915, since, until))
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#define IS_ADLS_GT_STEPPING(__i915, since, until) \
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#define IS_ADLS_GT_STEP(__i915, since, until) \
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(IS_ALDERLAKE_S(__i915) && \
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(IS_ALDERLAKE_S(__i915) && \
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IS_GT_STEP(__i915, since, until))
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IS_GT_STEP(__i915, since, until))
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@ -251,7 +251,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
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enum pipe pipe;
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enum pipe pipe;
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/* Wa_14011765242: adl-s A0 */
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/* Wa_14011765242: adl-s A0 */
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if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
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if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
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for_each_pipe(dev_priv, pipe)
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for_each_pipe(dev_priv, pipe)
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runtime->num_scalers[pipe] = 0;
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runtime->num_scalers[pipe] = 0;
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else if (INTEL_GEN(dev_priv) >= 10) {
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else if (INTEL_GEN(dev_priv) >= 10) {
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@ -7134,7 +7134,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
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ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/* Wa_1409825376:tgl (pre-prod)*/
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/* Wa_1409825376:tgl (pre-prod)*/
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if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
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if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
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intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
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intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
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TGL_VRH_GATING_DIS);
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TGL_VRH_GATING_DIS);
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