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dt-bindings: net: add DT bindings for Microsemi MIIM

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DT bindings for the Microsemi MII Management Controller found on Microsemi
SoCs

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexandre Belloni 2018-05-14 22:04:54 +02:00 committed by David S. Miller
parent 961423f9fc
commit cd1436a267
1 changed files with 26 additions and 0 deletions
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Documentation/devicetree/bindings/net/mscc-miim.txt Normal file
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Microsemi MII Management Controller (MIIM) / MDIO
=================================================
Properties:
- compatible: must be "mscc,ocelot-miim"
- reg: The base address of the MDIO bus controller register bank. Optionally, a
second register bank can be defined if there is an associated reset register
for internal PHYs
- #address-cells: Must be <1>.
- #size-cells: Must be <0>. MDIO addresses have no size component.
- interrupts: interrupt specifier (refer to the interrupt binding)
Typically an MDIO bus might have several children.
Example:
mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x36>, <0x10700f0 0x8>;
interrupts = <14>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};