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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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RISC-V Fixes for 6.5-rc7
* A fix to avoid excessive rejections from seccomp RET_ERRNO rules. * A fix for compressed jal/jalr decoding. * A pair of fixes for independent irq/softirq stacks on kernels built with CONFIG_FRAME_POINTER=n. * A fix to avoid a hang handling uaccess fixups. * Another build fix for toolchain ISA strings, this time for Zicsr and Zifenci on old GNU toolchains. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmTfa34THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYidwxD/9EeVWNnjAzZyz6dKtQRFe4czuQepXI 5Apcc8UKUs2vFfWybAAL8ICyzZ0ME8Vc+UfAZkFhouCBHpxMWmPDpkGiGxwKYw+E hWZeyIC8Vn/3mmdEvUVrFU37uyndhRaej6sJQb8tj2SLo4K3PvUELl6fhnSs2ESk EaSaOtTnC3DLKpJTup0jvCa1T9aGwVpEVuc7yjARiAxAquxH5ky6N5/l3gCGTQzJ Yph/llxhwmR83zwqto5kHS9nCWi6noammBCYl+Kbb7jMg6UMMBK6T3Dube5rvyqd 7ZEQNWAQ2RDs5pQJklutYjSCE+5LjONMX7IlrBR3plAMfXiLx+K3FhuMizHKD0YZ EIQ1QtsEuu6xPPZXig4KViEp75fRGnV6xJApAE0o0fUCJ7r77vddUJQDQdN3HhGe qfo8sEub8eWZ/IklkVhr6zsZAqMx6srb9r+T/iT+9KW9HKDNfNdEHc8FLuMjzm+C tIrrcZE40N7d37KVB/myWeDBrYAx6Bd6YaJOnuAR8H2t1dSj9rvxi7XFHfVdyRTs SUBQ0BCdMV+1UYmU1qtqWpti06nepeY3EMm4JLUFvKP+7jHBEcEwoye6/hGiTu7d rNsh6kB1Qq29JNQSn5HsOl89QRfz7orRGVZhTW9clhxrgV9fmy+pW9UG564NSSKI tBQGCt7OvXVMsQ== =LtPj -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - avoid excessive rejections from seccomp RET_ERRNO rules - compressed jal/jalr decoding fix - fixes for independent irq/softirq stacks on kernels built with CONFIG_FRAME_POINTER=n - avoid a hang handling uaccess fixups - another build fix for toolchain ISA strings, this time for Zicsr and Zifenci on old GNU toolchains * tag 'riscv-for-linus-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Handle zicsr/zifencei issue between gcc and binutils riscv: uaccess: Return the number of bytes effectively not copied riscv: stack: Fixup independent softirq stack for CONFIG_FRAME_POINTER=n riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=n riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() riscv: entry: set a0 = -ENOSYS only when syscall != -1
This commit is contained in:
Linus Torvalds
commit
cd479d9c72
6 changed files with 53 additions and 21 deletions
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@ -570,24 +570,30 @@ config TOOLCHAIN_HAS_ZIHINTPAUSE
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config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
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def_bool y
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# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
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depends on AS_IS_GNU && AS_VERSION >= 23800
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# https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
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depends on AS_IS_GNU && AS_VERSION >= 23600
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help
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Newer binutils versions default to ISA spec version 20191213 which
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moves some instructions from the I extension to the Zicsr and Zifencei
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extensions.
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Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer
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20191213 version, which moves some instructions from the I extension to
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the Zicsr and Zifencei extensions. This requires explicitly specifying
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Zicsr and Zifencei when binutils >= 2.38 or GCC >= 12.1.0. Zicsr
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and Zifencei are supported in binutils from version 2.36 onwards.
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To make life easier, and avoid forcing toolchains that default to a
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newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
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For clang < 17 or GCC < 11.1.0, for which this is not possible, this is
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dealt with in CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
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config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
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def_bool y
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depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
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# https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
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depends on CC_IS_CLANG && CLANG_VERSION < 170000
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# https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49
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depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110100)
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help
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Certain versions of clang do not support zicsr and zifencei via -march
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but newer versions of binutils require it for the reasons noted in the
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help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This
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option causes an older ISA spec compatible with these older versions
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of clang to be passed to GAS, which has the same result as passing zicsr
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and zifencei to -march.
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Certain versions of clang and GCC do not support zicsr and zifencei via
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-march. This option causes an older ISA spec compatible with these older
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versions of clang and GCC to be passed to GAS, which has the same result
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as passing zicsr and zifencei to -march.
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config FPU
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bool "FPU support"
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@ -110,6 +110,7 @@
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#define RVC_INSN_FUNCT4_OPOFF 12
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#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
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#define RVC_INSN_FUNCT3_OPOFF 13
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#define RVC_INSN_J_RS1_MASK GENMASK(11, 7)
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#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
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#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
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#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
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@ -245,8 +246,6 @@ __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
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__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
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__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
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__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
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__RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)
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__RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)
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__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
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__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
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__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
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@ -273,6 +272,18 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
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return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
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}
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static __always_inline bool riscv_insn_is_c_jr(u32 code)
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{
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return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
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(code & RVC_INSN_J_RS1_MASK) != 0;
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}
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static __always_inline bool riscv_insn_is_c_jalr(u32 code)
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{
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return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
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(code & RVC_INSN_J_RS1_MASK) != 0;
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}
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
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#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
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@ -11,7 +11,13 @@ compat_vdso-syms += flush_icache
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COMPAT_CC := $(CC)
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COMPAT_LD := $(LD)
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COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
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# binutils 2.35 does not support the zifencei extension, but in the ISA
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# spec 20191213, G stands for IMAFD_ZICSR_ZIFENCEI.
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ifdef CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
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COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
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else
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COMPAT_CC_FLAGS := -march=rv32imafd -mabi=ilp32
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endif
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COMPAT_LD_FLAGS := -melf32lriscv
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# Disable attributes, as they're useless and break the build.
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@ -84,6 +84,9 @@ void do_softirq_own_stack(void)
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: [sp] "r" (sp)
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: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6",
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#ifndef CONFIG_FRAME_POINTER
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"s0",
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#endif
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"memory");
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} else
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#endif
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@ -297,7 +297,7 @@ asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs)
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asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
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{
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if (user_mode(regs)) {
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ulong syscall = regs->a7;
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long syscall = regs->a7;
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regs->epc += 4;
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regs->orig_a0 = regs->a0;
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@ -306,9 +306,9 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
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syscall = syscall_enter_from_user_mode(regs, syscall);
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if (syscall < NR_syscalls)
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if (syscall >= 0 && syscall < NR_syscalls)
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syscall_handler(regs, syscall);
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else
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else if (syscall != -1)
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regs->a0 = -ENOSYS;
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syscall_exit_to_user_mode(regs);
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@ -372,6 +372,9 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs)
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: [sp] "r" (sp), [regs] "r" (regs)
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: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6",
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#ifndef CONFIG_FRAME_POINTER
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"s0",
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#endif
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"memory");
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} else
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#endif
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@ -17,8 +17,11 @@ ENTRY(__asm_copy_from_user)
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li t6, SR_SUM
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csrs CSR_STATUS, t6
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/* Save for return value */
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mv t5, a2
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/*
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* Save the terminal address which will be used to compute the number
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* of bytes copied in case of a fixup exception.
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*/
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add t5, a0, a2
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/*
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* Register allocation for code below:
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@ -176,7 +179,7 @@ ENTRY(__asm_copy_from_user)
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10:
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/* Disable access to user memory */
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csrc CSR_STATUS, t6
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mv a0, t5
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sub a0, t5, a0
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ret
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ENDPROC(__asm_copy_to_user)
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ENDPROC(__asm_copy_from_user)
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@ -228,7 +231,7 @@ ENTRY(__clear_user)
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11:
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/* Disable access to user memory */
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csrc CSR_STATUS, t6
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mv a0, a1
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sub a0, a3, a0
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ret
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ENDPROC(__clear_user)
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EXPORT_SYMBOL(__clear_user)
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