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x86/cpu: Add MSR numbers for FRED configuration
Add MSR numbers for the FRED configuration registers per FRED spec 5.0. Originally-by: Megha Dey <megha.dey@intel.com> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Shan Kang <shan.kang@intel.com> Link: https://lore.kernel.org/r/20231205105030.8698-13-xin3.li@intel.com
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2 changed files with 24 additions and 2 deletions
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/* Intel MSRs. Some also available on other CPUs */
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/* FRED MSRs */
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#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
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#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
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#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
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#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
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#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
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#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
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#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
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#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
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#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
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#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_TEST_CTRL 0x00000033
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#define MSR_TEST_CTRL 0x00000033
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/* Intel MSRs. Some also available on other CPUs */
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/* FRED MSRs */
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#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
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#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
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#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
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#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
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#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
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#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
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#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
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#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
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#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
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#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_TEST_CTRL 0x00000033
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#define MSR_TEST_CTRL 0x00000033
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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