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mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly
When ECC is not selected, the ECC enable bit must be cleared in the NAND control register. Same applies to DMA. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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1 changed files with 11 additions and 2 deletions
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@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
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uint32_t ndcr;
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ndcr = host->reg_ndcr;
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ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
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ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
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if (info->use_ecc)
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ndcr |= NDCR_ECC_EN;
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else
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ndcr &= ~NDCR_ECC_EN;
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if (info->use_dma)
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ndcr |= NDCR_DMA_EN;
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else
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ndcr &= ~NDCR_DMA_EN;
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ndcr |= NDCR_ND_RUN;
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/* clear status bits and run */
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