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clk: meson: axg-audio: separate axg and g12a regmap tables 

There are more differences than what we initially thought.
Let's keeps things clear and separate the axg and g12a regmap tables of the
audio clock controller.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-3-jbrunet@baylibre.com
This commit is contained in:
Jerome Brunet 2020-07-29 17:43:58 +02:00
parent 7b70689b07
commit cdabb1ffc7
1 changed files with 127 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

135
drivers/clk/meson/axg-audio.c
View File

@ -1209,13 +1209,132 @@ static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
};
/* Convenience table to populate regmap in .probe()
* Note that this table is shared between both AXG and G12A,
* with spdifout_b clocks being exclusive to G12A. Since those
* clocks are not declared within the AXG onecell table, we do not
* feel the need to have separate AXG/G12A regmap tables.
*/
/* Convenience table to populate regmap in .probe(). */
static struct clk_regmap *const axg_clk_regmaps[] = {
&ddr_arb,
&pdm,
&tdmin_a,
&tdmin_b,
&tdmin_c,
&tdmin_lb,
&tdmout_a,
&tdmout_b,
&tdmout_c,
&frddr_a,
&frddr_b,
&frddr_c,
&toddr_a,
&toddr_b,
&toddr_c,
&loopback,
&spdifin,
&spdifout,
&resample,
&power_detect,
&mst_a_mclk_sel,
&mst_b_mclk_sel,
&mst_c_mclk_sel,
&mst_d_mclk_sel,
&mst_e_mclk_sel,
&mst_f_mclk_sel,
&mst_a_mclk_div,
&mst_b_mclk_div,
&mst_c_mclk_div,
&mst_d_mclk_div,
&mst_e_mclk_div,
&mst_f_mclk_div,
&mst_a_mclk,
&mst_b_mclk,
&mst_c_mclk,
&mst_d_mclk,
&mst_e_mclk,
&mst_f_mclk,
&spdifout_clk_sel,
&spdifout_clk_div,
&spdifout_clk,
&spdifin_clk_sel,
&spdifin_clk_div,
&spdifin_clk,
&pdm_dclk_sel,
&pdm_dclk_div,
&pdm_dclk,
&pdm_sysclk_sel,
&pdm_sysclk_div,
&pdm_sysclk,
&mst_a_sclk_pre_en,
&mst_b_sclk_pre_en,
&mst_c_sclk_pre_en,
&mst_d_sclk_pre_en,
&mst_e_sclk_pre_en,
&mst_f_sclk_pre_en,
&mst_a_sclk_div,
&mst_b_sclk_div,
&mst_c_sclk_div,
&mst_d_sclk_div,
&mst_e_sclk_div,
&mst_f_sclk_div,
&mst_a_sclk_post_en,
&mst_b_sclk_post_en,
&mst_c_sclk_post_en,
&mst_d_sclk_post_en,
&mst_e_sclk_post_en,
&mst_f_sclk_post_en,
&mst_a_sclk,
&mst_b_sclk,
&mst_c_sclk,
&mst_d_sclk,
&mst_e_sclk,
&mst_f_sclk,
&mst_a_lrclk_div,
&mst_b_lrclk_div,
&mst_c_lrclk_div,
&mst_d_lrclk_div,
&mst_e_lrclk_div,
&mst_f_lrclk_div,
&mst_a_lrclk,
&mst_b_lrclk,
&mst_c_lrclk,
&mst_d_lrclk,
&mst_e_lrclk,
&mst_f_lrclk,
&tdmin_a_sclk_sel,
&tdmin_b_sclk_sel,
&tdmin_c_sclk_sel,
&tdmin_lb_sclk_sel,
&tdmout_a_sclk_sel,
&tdmout_b_sclk_sel,
&tdmout_c_sclk_sel,
&tdmin_a_sclk_pre_en,
&tdmin_b_sclk_pre_en,
&tdmin_c_sclk_pre_en,
&tdmin_lb_sclk_pre_en,
&tdmout_a_sclk_pre_en,
&tdmout_b_sclk_pre_en,
&tdmout_c_sclk_pre_en,
&tdmin_a_sclk_post_en,
&tdmin_b_sclk_post_en,
&tdmin_c_sclk_post_en,
&tdmin_lb_sclk_post_en,
&tdmout_a_sclk_post_en,
&tdmout_b_sclk_post_en,
&tdmout_c_sclk_post_en,
&tdmin_a_sclk,
&tdmin_b_sclk,
&tdmin_c_sclk,
&tdmin_lb_sclk,
&tdmout_a_sclk,
&tdmout_b_sclk,
&tdmout_c_sclk,
&tdmin_a_lrclk,
&tdmin_b_lrclk,
&tdmin_c_lrclk,
&tdmin_lb_lrclk,
&tdmout_a_lrclk,
&tdmout_b_lrclk,
&tdmout_c_lrclk,
};
static struct clk_regmap *const g12a_clk_regmaps[] = {
&ddr_arb,
&pdm,
&tdmin_a,
@ -1713,8 +1832,8 @@ static const struct audioclk_data axg_audioclk_data = {
};
static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_onecell_data = &g12a_audio_hw_onecell_data,
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,