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[WATCHDOG] i6300esb-set_correct_reload_register_bit

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This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.

Signed-off-by: Naveen Gupta <ngupta@google.com>
Signed-off-by: David Hardeman <david@2gen.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Andrew Morton <akpm@osdl.org>
This commit is contained in:
Naveen Gupta 2005-08-17 09:11:46 +02:00 committed by Wim Van Sebroeck
parent 28562af3d4
commit ce2f50b4ae
2 changed files with 5 additions and 3 deletions
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6
drivers/char/watchdog/i6300esb.c
View file

@ -109,7 +109,7 @@ static int esb_timer_stop(void)
spin_lock(&esb_lock);
/* First, reset timers as suggested by the docs */
esb_unlock_registers();
writew(0x10, ESB_RELOAD_REG);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* Then disable the WDT */
pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@ -123,7 +123,7 @@ static void esb_timer_keepalive(void)
{
spin_lock(&esb_lock);
esb_unlock_registers();
writew(0x10, ESB_RELOAD_REG);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush anything here? */
spin_unlock(&esb_lock);
}
@ -153,7 +153,7 @@ static int esb_timer_set_heartbeat(int time)
/* Reload */
esb_unlock_registers();
writew(0x10, ESB_RELOAD_REG);
writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush everything out? */

2
drivers/char/watchdog/i6300esb.h
View file

@ -54,6 +54,8 @@
#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
/* Reload register bits */
#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
/*
* Some magic constants