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Merge branch 'remotes/lorenzo/pci/aardvark'
- Remove Aardvark outbound window configuration (Evan Wang) - Fix Aardvark bridge window sizing issue (Zachary Zhang) - Convert Aardvark to use pci_host_probe() to reduce code duplication (Thomas Petazzoni) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Convert to use pci_host_probe() PCI: aardvark: Size bridges before resources allocation PCI: aardvark: Remove PCIe outbound window configuration PCI: aardvark: Introduce an advk_pcie_valid_device() helper # Conflicts: # drivers/pci/controller/pci-aardvark.c
This commit is contained in:
commit
ce342a1aa8
1 changed files with 12 additions and 67 deletions
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@ -111,24 +111,6 @@
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#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
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#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
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/* PCIe window configuration */
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#define OB_WIN_BASE_ADDR 0x4c00
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#define OB_WIN_BLOCK_SIZE 0x20
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#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
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OB_WIN_BLOCK_SIZE * (win) + \
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(offset))
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#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
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#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
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#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
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#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
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#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
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#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
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#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
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/* PCIe window types */
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#define OB_PCIE_MEM 0x0
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#define OB_PCIE_IO 0x4
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/* LMI registers base address and register offsets */
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#define LMI_BASE_ADDR 0x6000
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#define CFG_REG (LMI_BASE_ADDR + 0x0)
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@ -247,34 +229,9 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
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return -ETIMEDOUT;
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}
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/*
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* Set PCIe address window register which could be used for memory
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* mapping.
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*/
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static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
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u32 win_num, u32 match_ms,
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u32 match_ls, u32 mask_ms,
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u32 mask_ls, u32 remap_ms,
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u32 remap_ls, u32 action)
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{
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advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
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advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
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advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
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advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
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advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
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advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
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advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
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advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
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}
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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u32 reg;
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int i;
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/* Point PCIe unit MBUS decode windows to DRAM space */
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for (i = 0; i < 8; i++)
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advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
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/* Set to Direct mode */
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reg = advk_readl(pcie, CTRL_CONFIG_REG);
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@ -433,6 +390,15 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
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return -ETIMEDOUT;
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}
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static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
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int devfn)
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{
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if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
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return false;
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return true;
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}
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static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 *val)
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{
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@ -440,7 +406,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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u32 reg;
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int ret;
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if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) {
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if (!advk_pcie_valid_device(pcie, bus, devfn)) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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@ -494,7 +460,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int offset;
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int ret;
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if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
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if (!advk_pcie_valid_device(pcie, bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (where % size)
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@ -843,12 +809,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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switch (resource_type(res)) {
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case IORESOURCE_IO:
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advk_pcie_set_ob_win(pcie, 1,
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upper_32_bits(res->start),
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lower_32_bits(res->start),
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0, 0xF8000000, 0,
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lower_32_bits(res->start),
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OB_PCIE_IO);
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err = devm_pci_remap_iospace(dev, res, iobase);
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if (err) {
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dev_warn(dev, "error %d: failed to map resource %pR\n",
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@ -857,12 +817,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
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}
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break;
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case IORESOURCE_MEM:
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advk_pcie_set_ob_win(pcie, 0,
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upper_32_bits(res->start),
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lower_32_bits(res->start),
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0x0, 0xF8000000, 0,
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lower_32_bits(res->start),
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(2 << 20) | OB_PCIE_MEM);
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res_valid |= !(res->flags & IORESOURCE_PREFETCH);
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break;
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case IORESOURCE_BUS:
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@ -889,7 +843,6 @@ static int advk_pcie_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct advk_pcie *pcie;
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struct resource *res;
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struct pci_bus *bus, *child;
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struct pci_host_bridge *bridge;
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int ret, irq;
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@ -943,21 +896,13 @@ static int advk_pcie_probe(struct platform_device *pdev)
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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ret = pci_scan_root_bus_bridge(bridge);
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ret = pci_host_probe(bridge);
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if (ret < 0) {
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advk_pcie_remove_msi_irq_domain(pcie);
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advk_pcie_remove_irq_domain(pcie);
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return ret;
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}
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bus = bridge->bus;
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pci_bus_assign_resources(bus);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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pci_bus_add_devices(bus);
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return 0;
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}
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