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drm/amdgpu: Add APU support in vi_set_uvd_clocks
commit 819a23f83e
upstream.
fix the issue set uvd clock failed on CZ/ST
which lead 1s delay when boot up.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
b141de45e2
commit
ce686c4247
1 changed files with 35 additions and 11 deletions
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@ -729,33 +729,57 @@ static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
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return r;
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tmp = RREG32_SMC(cntl_reg);
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tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
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CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
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if (adev->flags & AMD_IS_APU)
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tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
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else
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tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
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CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
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tmp |= dividers.post_divider;
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WREG32_SMC(cntl_reg, tmp);
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for (i = 0; i < 100; i++) {
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if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
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break;
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tmp = RREG32_SMC(status_reg);
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if (adev->flags & AMD_IS_APU) {
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if (tmp & 0x10000)
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break;
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} else {
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if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
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break;
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}
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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return 0;
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}
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#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
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#define ixGNB_CLK1_STATUS 0xD822010C
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#define ixGNB_CLK2_DFS_CNTL 0xD8220110
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#define ixGNB_CLK2_STATUS 0xD822012C
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static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
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{
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int r;
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r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
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if (r)
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return r;
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if (adev->flags & AMD_IS_APU) {
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r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
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if (r)
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return r;
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r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
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if (r)
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return r;
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r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
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if (r)
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return r;
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} else {
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r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
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if (r)
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return r;
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r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
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if (r)
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return r;
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}
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return 0;
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}
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