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drm/amd/display: Fix DP2.0 timing sync
[Why] Triggering OTG sync before all OTG/HPO clock programming is complete causes timing sync to fail and a subsequent P-state hang. [How] Move DTB clock programming earlier in the sequence to enable_stream_timing. Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1288d70208
commit
ce74bece80
5 changed files with 55 additions and 31 deletions
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@ -670,6 +670,37 @@ static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
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return flow_ctrl_cnt;
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}
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static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
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{
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switch (link->link_enc->transmitter) {
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case TRANSMITTER_UNIPHY_A:
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return PHYD32CLKA;
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case TRANSMITTER_UNIPHY_B:
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return PHYD32CLKB;
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case TRANSMITTER_UNIPHY_C:
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return PHYD32CLKC;
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case TRANSMITTER_UNIPHY_D:
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return PHYD32CLKD;
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case TRANSMITTER_UNIPHY_E:
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return PHYD32CLKE;
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default:
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return PHYD32CLKA;
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}
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}
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static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
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{
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struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
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int count = 1;
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while (odm_pipe != NULL) {
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count++;
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odm_pipe = odm_pipe->next_odm_pipe;
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}
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return count;
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}
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enum dc_status dcn20_enable_stream_timing(
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context,
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@ -817,6 +848,23 @@ enum dc_status dcn20_enable_stream_timing(
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if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
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pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
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}
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if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
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struct dccg *dccg = dc->res_pool->dccg;
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struct timing_generator *tg = pipe_ctx->stream_res.tg;
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struct dtbclk_dto_params dto_params = {0};
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if (dccg->funcs->set_dtbclk_p_src)
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dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);
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dto_params.otg_inst = tg->inst;
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dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
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dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
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dto_params.timing = &pipe_ctx->stream->timing;
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dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
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dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
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}
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return DC_OK;
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}
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@ -2659,37 +2707,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
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hubp->mpcc_id = mpcc_id;
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}
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static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
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{
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switch (link->link_enc->transmitter) {
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case TRANSMITTER_UNIPHY_A:
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return PHYD32CLKA;
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case TRANSMITTER_UNIPHY_B:
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return PHYD32CLKB;
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case TRANSMITTER_UNIPHY_C:
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return PHYD32CLKC;
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case TRANSMITTER_UNIPHY_D:
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return PHYD32CLKD;
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case TRANSMITTER_UNIPHY_E:
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return PHYD32CLKE;
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default:
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return PHYD32CLKA;
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}
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}
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static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
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{
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struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
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int count = 1;
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while (odm_pipe != NULL) {
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count++;
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odm_pipe = odm_pipe->next_odm_pipe;
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}
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return count;
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}
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void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
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{
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enum dc_lane_count lane_count =
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@ -375,6 +375,7 @@ static const struct dccg_funcs dccg314_funcs = {
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.set_pixel_rate_div = dccg314_set_pixel_rate_div,
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.trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,
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.set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
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.set_dtbclk_p_src = dccg314_set_dtbclk_p_src
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};
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struct dccg *dccg314_create(
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@ -345,6 +345,7 @@ static const struct dccg_funcs dccg32_funcs = {
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.otg_drop_pixel = dccg32_otg_drop_pixel,
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.set_pixel_rate_div = dccg32_set_pixel_rate_div,
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.trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,
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.set_dtbclk_p_src = dccg32_set_dtbclk_p_src,
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};
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struct dccg *dccg32_create(
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@ -767,6 +767,7 @@ static const struct dccg_funcs dccg35_funcs = {
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.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,
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.enable_symclk_se = dccg35_enable_symclk_se,
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.disable_symclk_se = dccg35_disable_symclk_se,
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.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
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};
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struct dccg *dccg35_create(
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@ -192,6 +192,10 @@ struct dccg_funcs {
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void (*set_dp_dto)(
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struct dccg *dccg,
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const struct dp_dto_params *params);
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void (*set_dtbclk_p_src)(
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struct dccg *dccg,
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enum streamclk_source src,
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uint32_t otg_inst);
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};
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#endif //__DAL_DCCG_H__
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