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soc: renesas: rcar-sysc: Improve SYSC interrupt config in legacy wrapper
Align SYSC interrupt configuration in the legacy wrapper with the DT version: - Mask SYSC interrupt sources before enabling them (doesn't matter much as they're disabled at the GIC level anyway), - Make sure not to clear reserved SYSCIMR bits that were set before. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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1 changed files with 15 additions and 2 deletions
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@ -402,12 +402,25 @@ early_initcall(rcar_sysc_pd_init);
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void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
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void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
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{
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{
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u32 syscimr;
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if (!rcar_sysc_pd_init())
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if (!rcar_sysc_pd_init())
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return;
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return;
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rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
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rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
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/* enable all interrupt sources, but do not use interrupt handler */
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/*
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* Mask all interrupt sources to prevent the CPU from receiving them.
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* Make sure not to clear reserved bits that were set before.
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*/
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syscimr = ioread32(rcar_sysc_base + SYSCIMR);
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syscimr |= syscier;
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pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
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iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
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/*
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* SYSC needs all interrupt sources enabled to control power.
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*/
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pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
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iowrite32(syscier, rcar_sysc_base + SYSCIER);
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iowrite32(syscier, rcar_sysc_base + SYSCIER);
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iowrite32(0, rcar_sysc_base + SYSCIMR);
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}
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}
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