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qed: Add support for Timestamping the unicast PTP packets.
This patch adds driver changes to detect/timestamp the unicast PTP packets. Changes from previous version: ------------------------------- v2: Defined a macro for unicast ptp param mask. Please consider applying this to "net-next". Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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cedeac9df4
1 changed files with 6 additions and 2 deletions
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@ -44,6 +44,8 @@
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/* Add/subtract the Adjustment_Value when making a Drift adjustment */
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/* Add/subtract the Adjustment_Value when making a Drift adjustment */
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#define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
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#define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
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#define QED_TIMESTAMP_MASK BIT(16)
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#define QED_TIMESTAMP_MASK BIT(16)
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/* Param mask for Hardware to detect/timestamp the unicast PTP packets */
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#define QED_PTP_UCAST_PARAM_MASK 0xF
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static enum qed_resc_lock qed_ptcdev_to_resc(struct qed_hwfn *p_hwfn)
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static enum qed_resc_lock qed_ptcdev_to_resc(struct qed_hwfn *p_hwfn)
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{
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{
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@ -243,7 +245,8 @@ static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
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return -EINVAL;
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return -EINVAL;
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}
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK,
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QED_PTP_UCAST_PARAM_MASK);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
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@ -253,7 +256,8 @@ static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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} else {
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} else {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK,
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QED_PTP_UCAST_PARAM_MASK);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
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}
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}
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