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pinctrl: intel: Make offset to interrupt status register configurable
Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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parent
1396007286
commit
cf769bd86b
2 changed files with 15 additions and 8 deletions
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@ -30,8 +30,6 @@
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#define PADBAR 0x00c
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#define GPI_IS 0x100
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#define GPI_GPE_STS 0x140
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#define GPI_GPE_EN 0x160
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#define PADOWN_BITS 4
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#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
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@ -818,7 +816,7 @@ static void intel_gpio_irq_ack(struct irq_data *d)
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community = intel_get_community(pctrl, pin);
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if (community) {
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const struct intel_padgroup *padgrp;
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unsigned gpp, gpp_offset;
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unsigned gpp, gpp_offset, is_offset;
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padgrp = intel_community_get_padgroup(community, pin);
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if (!padgrp)
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@ -826,9 +824,10 @@ static void intel_gpio_irq_ack(struct irq_data *d)
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gpp = padgrp->reg_num;
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gpp_offset = padgroup_offset(padgrp, pin);
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is_offset = community->is_offset + gpp * 4;
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raw_spin_lock(&pctrl->lock);
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writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
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writel(BIT(gpp_offset), community->regs + is_offset);
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raw_spin_unlock(&pctrl->lock);
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}
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}
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@ -843,7 +842,7 @@ static void intel_gpio_irq_enable(struct irq_data *d)
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community = intel_get_community(pctrl, pin);
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if (community) {
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const struct intel_padgroup *padgrp;
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unsigned gpp, gpp_offset;
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unsigned gpp, gpp_offset, is_offset;
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unsigned long flags;
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u32 value;
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@ -853,10 +852,11 @@ static void intel_gpio_irq_enable(struct irq_data *d)
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gpp = padgrp->reg_num;
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gpp_offset = padgroup_offset(padgrp, pin);
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is_offset = community->is_offset + gpp * 4;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* Clear interrupt status first to avoid unexpected interrupt */
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writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
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writel(BIT(gpp_offset), community->regs + is_offset);
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value = readl(community->regs + community->ie_offset + gpp * 4);
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value |= BIT(gpp_offset);
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@ -991,7 +991,8 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
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const struct intel_padgroup *padgrp = &community->gpps[gpp];
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unsigned long pending, enabled, gpp_offset;
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pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);
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pending = readl(community->regs + community->is_offset +
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padgrp->reg_num * 4);
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enabled = readl(community->regs + community->ie_offset +
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padgrp->reg_num * 4);
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@ -1241,6 +1242,9 @@ int intel_pinctrl_probe(struct platform_device *pdev,
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community->regs = regs;
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community->pad_regs = regs + padbar;
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if (!community->is_offset)
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community->is_offset = GPI_IS;
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ret = intel_pinctrl_add_padgroups(pctrl, community);
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if (ret)
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return ret;
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@ -1356,7 +1360,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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/* Mask and clear all interrupts */
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writel(0, base + community->ie_offset + gpp * 4);
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writel(0xffff, base + GPI_IS + gpp * 4);
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writel(0xffff, base + community->is_offset + gpp * 4);
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}
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}
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}
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@ -73,6 +73,8 @@ struct intel_padgroup {
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* @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
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* is assumed that the host owns the pin (rather than
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* ACPI).
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* @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
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* default (%0x100).
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* @ie_offset: Register offset of GPI_IE from @regs.
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* @pin_base: Starting pin of pins in this community
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* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
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@ -98,6 +100,7 @@ struct intel_community {
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unsigned padown_offset;
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unsigned padcfglock_offset;
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unsigned hostown_offset;
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unsigned is_offset;
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unsigned ie_offset;
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unsigned pin_base;
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unsigned gpp_size;
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