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crypto: hisilicon/hpre - save capability registers in probe process
Pre-store the valid value of hpre alg support related capability
register in hpre_qm_init(), which will be called by hpre_probe().
It can reduce the number of capability register queries and avoid
obtaining incorrect values in abnormal scenarios, such as reset
failed and the memory space disabled.
Fixes: f214d59a06
("crypto: hisilicon/hpre - support hpre capability")
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
cabe13d0bd
commit
cf8b5156bb
1 changed files with 64 additions and 18 deletions
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@ -226,6 +226,20 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = {
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{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
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{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
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};
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};
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enum hpre_pre_store_cap_idx {
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HPRE_CLUSTER_NUM_CAP_IDX = 0x0,
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HPRE_CORE_ENABLE_BITMAP_CAP_IDX,
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HPRE_DRV_ALG_BITMAP_CAP_IDX,
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HPRE_DEV_ALG_BITMAP_CAP_IDX,
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};
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static const u32 hpre_pre_store_caps[] = {
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HPRE_CLUSTER_NUM_CAP,
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HPRE_CORE_ENABLE_BITMAP_CAP,
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HPRE_DRV_ALG_BITMAP_CAP,
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HPRE_DEV_ALG_BITMAP_CAP,
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};
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static const struct hpre_hw_error hpre_hw_errors[] = {
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static const struct hpre_hw_error hpre_hw_errors[] = {
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{
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{
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.int_msk = BIT(0),
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.int_msk = BIT(0),
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@ -348,7 +362,7 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
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{
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{
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u32 cap_val;
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u32 cap_val;
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cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);
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cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;
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if (alg & cap_val)
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if (alg & cap_val)
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return true;
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return true;
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@ -424,16 +438,6 @@ static u32 vfs_num;
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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static inline int hpre_cluster_num(struct hisi_qm *qm)
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{
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return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver);
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}
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static inline int hpre_cluster_core_mask(struct hisi_qm *qm)
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{
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return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver);
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}
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struct hisi_qp *hpre_create_qp(u8 type)
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struct hisi_qp *hpre_create_qp(u8 type)
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{
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{
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int node = cpu_to_node(smp_processor_id());
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int node = cpu_to_node(smp_processor_id());
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@ -500,13 +504,15 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm)
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static int hpre_set_cluster(struct hisi_qm *qm)
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static int hpre_set_cluster(struct hisi_qm *qm)
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{
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{
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u32 cluster_core_mask = hpre_cluster_core_mask(qm);
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u8 clusters_num = hpre_cluster_num(qm);
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struct device *dev = &qm->pdev->dev;
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struct device *dev = &qm->pdev->dev;
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unsigned long offset;
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unsigned long offset;
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u32 cluster_core_mask;
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u8 clusters_num;
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u32 val = 0;
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u32 val = 0;
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int ret, i;
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int ret, i;
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cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val;
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clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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for (i = 0; i < clusters_num; i++) {
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offset = i * HPRE_CLSTR_ADDR_INTRVL;
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offset = i * HPRE_CLSTR_ADDR_INTRVL;
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@ -701,11 +707,12 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
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static void hpre_cnt_regs_clear(struct hisi_qm *qm)
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static void hpre_cnt_regs_clear(struct hisi_qm *qm)
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{
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{
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u8 clusters_num = hpre_cluster_num(qm);
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unsigned long offset;
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unsigned long offset;
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u8 clusters_num;
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int i;
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int i;
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/* clear clusterX/cluster_ctrl */
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/* clear clusterX/cluster_ctrl */
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clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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for (i = 0; i < clusters_num; i++) {
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offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
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offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
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writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
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writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
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@ -992,13 +999,14 @@ static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)
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static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
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static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
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{
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{
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u8 clusters_num = hpre_cluster_num(qm);
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struct device *dev = &qm->pdev->dev;
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struct device *dev = &qm->pdev->dev;
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char buf[HPRE_DBGFS_VAL_MAX_LEN];
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char buf[HPRE_DBGFS_VAL_MAX_LEN];
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struct debugfs_regset32 *regset;
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struct debugfs_regset32 *regset;
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struct dentry *tmp_d;
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struct dentry *tmp_d;
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u8 clusters_num;
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int i, ret;
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int i, ret;
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clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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for (i = 0; i < clusters_num; i++) {
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ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
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ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
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if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
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if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
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@ -1103,6 +1111,34 @@ static void hpre_debugfs_exit(struct hisi_qm *qm)
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debugfs_remove_recursive(qm->debug.debug_root);
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debugfs_remove_recursive(qm->debug.debug_root);
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}
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}
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static int hpre_pre_store_cap_reg(struct hisi_qm *qm)
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{
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struct hisi_qm_cap_record *hpre_cap;
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struct device *dev = &qm->pdev->dev;
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size_t i, size;
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size = ARRAY_SIZE(hpre_pre_store_caps);
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hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL);
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if (!hpre_cap)
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return -ENOMEM;
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for (i = 0; i < size; i++) {
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hpre_cap[i].type = hpre_pre_store_caps[i];
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hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,
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hpre_pre_store_caps[i], qm->cap_ver);
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}
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if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) {
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dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n",
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hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX);
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return -EINVAL;
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}
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qm->cap_tables.dev_cap_table = hpre_cap;
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return 0;
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}
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static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
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static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
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{
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{
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u64 alg_msk;
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u64 alg_msk;
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@ -1136,7 +1172,15 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
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return ret;
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return ret;
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}
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}
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alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
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/* Fetch and save the value of capability registers */
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ret = hpre_pre_store_cap_reg(qm);
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if (ret) {
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pci_err(pdev, "Failed to pre-store capability registers!\n");
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hisi_qm_uninit(qm);
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return ret;
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}
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alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;
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ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
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ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
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if (ret) {
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if (ret) {
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pci_err(pdev, "Failed to set hpre algs!\n");
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pci_err(pdev, "Failed to set hpre algs!\n");
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@ -1150,11 +1194,12 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm)
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{
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{
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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u8 clusters_num = hpre_cluster_num(qm);
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struct qm_debug *debug = &qm->debug;
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struct qm_debug *debug = &qm->debug;
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void __iomem *io_base;
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void __iomem *io_base;
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u8 clusters_num;
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int i, j, idx;
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int i, j, idx;
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clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
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debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
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com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
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com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
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if (!debug->last_words)
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if (!debug->last_words)
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@ -1191,10 +1236,10 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
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{
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{
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
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u8 clusters_num = hpre_cluster_num(qm);
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struct qm_debug *debug = &qm->debug;
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struct qm_debug *debug = &qm->debug;
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struct pci_dev *pdev = qm->pdev;
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struct pci_dev *pdev = qm->pdev;
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void __iomem *io_base;
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void __iomem *io_base;
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u8 clusters_num;
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int i, j, idx;
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int i, j, idx;
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u32 val;
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u32 val;
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@ -1209,6 +1254,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
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hpre_com_dfx_regs[i].name, debug->last_words[i], val);
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hpre_com_dfx_regs[i].name, debug->last_words[i], val);
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}
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}
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clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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for (i = 0; i < clusters_num; i++) {
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io_base = qm->io_base + hpre_cluster_offsets[i];
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io_base = qm->io_base + hpre_cluster_offsets[i];
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for (j = 0; j < cluster_dfx_regs_num; j++) {
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for (j = 0; j < cluster_dfx_regs_num; j++) {
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