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clk: rockchip: add clock controller for rk3568 

Add the clock tree definition for the new rk3568 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210315085608.16010-5-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Elaine Zhang 2021-03-15 16:56:08 +08:00 committed by Heiko Stuebner
parent a3561e77cf
commit cf911d89c4
4 changed files with 1762 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/clk/rockchip/Kconfig
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@ -85,4 +85,11 @@ config CLK_RK3399
default y
help
Build the driver for RK3399 Clock Driver.
config CLK_RK3568
tristate "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST
default y
help
Build the driver for RK3568 Clock Driver.
endif

1
drivers/clk/rockchip/Makefile
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@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o

1725
drivers/clk/rockchip/clk-rk3568.c Normal file
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File diff suppressed because it is too large Load Diff

30
drivers/clk/rockchip/clk.h
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@ -188,6 +188,34 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
#define RK3568_MISC_CON1 0xc8
#define RK3568_MISC_CON2 0xcc
#define RK3568_GLB_CNT_TH 0xd0
#define RK3568_GLB_SRST_FST 0xd4
#define RK3568_GLB_SRST_SND 0xd8
#define RK3568_GLB_RST_CON 0xdc
#define RK3568_GLB_RST_ST 0xe0
#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3568_SDMMC0_CON0 0x580
#define RK3568_SDMMC0_CON1 0x584
#define RK3568_SDMMC1_CON0 0x588
#define RK3568_SDMMC1_CON1 0x58c
#define RK3568_SDMMC2_CON0 0x590
#define RK3568_SDMMC2_CON1 0x594
#define RK3568_EMMC_CON0 0x598
#define RK3568_EMMC_CON1 0x59c
#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_PMU_MODE_CON0 0x80
#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
@ -322,7 +350,7 @@ struct rockchip_cpuclk_clksel {
u32 val;
};
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
#define ROCKCHIP_CPUCLK_MAX_CORES 4
struct rockchip_cpuclk_rate_table {
unsigned long prate;