dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping

Add the new binding documentation for MediaTek frequency hopping
and spread spectrum clocking control.

Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221121122957.21611-3-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
This commit is contained in:
Johnson Wang 2022-11-21 20:29:55 +08:00 committed by Chen-Yu Tsai
parent 029c936ae7
commit cfcefe36bf

View file

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek frequency hopping and spread spectrum clocking control
maintainers:
- Edward-JW Yang <edward-jw.yang@mediatek.com>
description: |
Frequency hopping control (FHCTL) is a piece of hardware that control
some PLLs to adopt "hopping" mechanism to adjust their frequency.
Spread spectrum clocking (SSC) is another function provided by this hardware.
properties:
compatible:
const: mediatek,mt8186-fhctl
reg:
maxItems: 1
clocks:
description: Phandles of the PLL with FHCTL hardware capability.
minItems: 1
maxItems: 30
mediatek,hopping-ssc-percent:
description: The percentage of spread spectrum clocking for one PLL.
minItems: 1
maxItems: 30
items:
default: 0
minimum: 0
maximum: 8
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8186-clk.h>
fhctl: fhctl@1000ce00 {
compatible = "mediatek,mt8186-fhctl";
reg = <0x1000ce00 0x200>;
clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
mediatek,hopping-ssc-percent = <3>;
};