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Merge tag 'amd-drm-fixes-5.11-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.11-2021-02-03: amdgpu: - Fix retry in gem create - Vangogh fixes - Fix for display from shared buffers - Various display fixes amdkfd: - Fix regression in buffer free Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210204041300.4425-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
cfd4951f93
12 changed files with 94 additions and 58 deletions
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@ -26,6 +26,7 @@
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#include <linux/sched/task.h>
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#include "amdgpu_object.h"
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#include "amdgpu_gem.h"
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#include "amdgpu_vm.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_dma_buf.h"
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@ -1152,7 +1153,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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struct sg_table *sg = NULL;
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uint64_t user_addr = 0;
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struct amdgpu_bo *bo;
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struct amdgpu_bo_param bp;
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struct drm_gem_object *gobj;
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u32 domain, alloc_domain;
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u64 alloc_flags;
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int ret;
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@ -1220,19 +1221,14 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
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va, size, domain_string(alloc_domain));
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = 1;
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bp.domain = alloc_domain;
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bp.flags = alloc_flags;
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bp.type = bo_type;
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bp.resv = NULL;
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ret = amdgpu_bo_create(adev, &bp, &bo);
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ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
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bo_type, NULL, &gobj);
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if (ret) {
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pr_debug("Failed to create BO on domain %s. ret %d\n",
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domain_string(alloc_domain), ret);
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domain_string(alloc_domain), ret);
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goto err_bo_create;
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}
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bo = gem_to_amdgpu_bo(gobj);
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if (bo_type == ttm_bo_type_sg) {
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bo->tbo.sg = sg;
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bo->tbo.ttm->sg = sg;
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@ -926,8 +926,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *file_priv,
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const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct drm_gem_object *obj;
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struct amdgpu_framebuffer *amdgpu_fb;
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struct drm_gem_object *obj;
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struct amdgpu_bo *bo;
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uint32_t domains;
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int ret;
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obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
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@ -938,7 +940,9 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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}
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/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
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if (obj->import_attach) {
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bo = gem_to_amdgpu_bo(obj);
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domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
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if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
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drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
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return ERR_PTR(-EINVAL);
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}
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@ -269,8 +269,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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resv = vm->root.base.bo->tbo.base.resv;
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}
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retry:
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initial_domain = (u32)(0xffffffff & args->in.domains);
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retry:
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r = amdgpu_gem_object_create(adev, size, args->in.alignment,
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initial_domain,
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flags, ttm_bo_type_device, resv, &gobj);
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@ -897,7 +897,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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return -EINVAL;
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/* A shared bo cannot be migrated to VRAM */
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if (bo->prime_shared_count) {
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if (bo->prime_shared_count || bo->tbo.base.import_attach) {
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if (domain & AMDGPU_GEM_DOMAIN_GTT)
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domain = AMDGPU_GEM_DOMAIN_GTT;
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else
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@ -99,6 +99,10 @@
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
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#define mmCGTS_TCC_DISABLE_Vangogh 0x5006
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#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007
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#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
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@ -4936,8 +4940,18 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
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{
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/* TCCs are global (not instanced). */
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uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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uint32_t tcc_disable;
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switch (adev->asic_type) {
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case CHIP_VANGOGH:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);
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break;
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default:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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break;
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}
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adev->gfx.config.tcc_disabled_mask =
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REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
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@ -1833,8 +1833,8 @@ static void emulated_link_detect(struct dc_link *link)
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link->type = dc_connection_none;
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prev_sink = link->local_sink;
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if (prev_sink != NULL)
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dc_sink_retain(prev_sink);
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if (prev_sink)
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dc_sink_release(prev_sink);
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switch (link->connector_signal) {
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case SIGNAL_TYPE_HDMI_TYPE_A: {
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@ -1934,7 +1934,7 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
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dc_commit_updates_for_stream(
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dm->dc, bundle->surface_updates,
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dc_state->stream_status->plane_count,
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dc_state->streams[k], &bundle->stream_update, dc_state);
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dc_state->streams[k], &bundle->stream_update);
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}
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cleanup:
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@ -1965,8 +1965,7 @@ static void dm_set_dpms_off(struct dc_link *link)
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stream_update.stream = stream_state;
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dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
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stream_state, &stream_update,
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stream_state->ctx->dc->current_state);
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stream_state, &stream_update);
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mutex_unlock(&adev->dm.dc_lock);
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}
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@ -2330,8 +2329,10 @@ void amdgpu_dm_update_connector_after_detect(
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* TODO: check if we still need the S3 mode update workaround.
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* If yes, put it here.
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*/
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if (aconnector->dc_sink)
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if (aconnector->dc_sink) {
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amdgpu_dm_update_freesync_caps(connector, NULL);
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dc_sink_release(aconnector->dc_sink);
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}
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aconnector->dc_sink = sink;
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dc_sink_retain(aconnector->dc_sink);
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@ -2347,8 +2348,6 @@ void amdgpu_dm_update_connector_after_detect(
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drm_connector_update_edid_property(connector,
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aconnector->edid);
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drm_add_edid_modes(connector, aconnector->edid);
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if (aconnector->dc_link->aux_mode)
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drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
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aconnector->edid);
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@ -7549,7 +7548,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct drm_crtc *pcrtc,
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bool wait_for_vblank)
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{
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uint32_t i;
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int i;
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uint64_t timestamp_ns;
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struct drm_plane *plane;
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struct drm_plane_state *old_plane_state, *new_plane_state;
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@ -7590,7 +7589,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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amdgpu_dm_commit_cursors(state);
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/* update planes when needed */
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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struct drm_crtc *crtc = new_plane_state->crtc;
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struct drm_crtc_state *new_crtc_state;
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struct drm_framebuffer *fb = new_plane_state->fb;
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@ -7813,8 +7812,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->surface_updates,
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planes_count,
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acrtc_state->stream,
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&bundle->stream_update,
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dc_state);
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&bundle->stream_update);
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/**
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* Enable or disable the interrupts on the backend.
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@ -8150,13 +8148,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
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struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
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struct dc_surface_update dummy_updates[MAX_SURFACES];
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struct dc_surface_update surface_updates[MAX_SURFACES];
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struct dc_stream_update stream_update;
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struct dc_info_packet hdr_packet;
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struct dc_stream_status *status = NULL;
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bool abm_changed, hdr_changed, scaling_changed;
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memset(&dummy_updates, 0, sizeof(dummy_updates));
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memset(&surface_updates, 0, sizeof(surface_updates));
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memset(&stream_update, 0, sizeof(stream_update));
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if (acrtc) {
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@ -8213,16 +8211,15 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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* To fix this, DC should permit updating only stream properties.
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*/
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for (j = 0; j < status->plane_count; j++)
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dummy_updates[j].surface = status->plane_states[0];
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surface_updates[j].surface = status->plane_states[j];
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mutex_lock(&dm->dc_lock);
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dc_commit_updates_for_stream(dm->dc,
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dummy_updates,
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surface_updates,
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status->plane_count,
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dm_new_crtc_state->stream,
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&stream_update,
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dc_state);
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&stream_update);
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mutex_unlock(&dm->dc_lock);
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}
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@ -8359,14 +8356,14 @@ static int dm_force_atomic_commit(struct drm_connector *connector)
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ret = PTR_ERR_OR_ZERO(conn_state);
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if (ret)
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goto err;
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goto out;
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/* Attach crtc to drm_atomic_state*/
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crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
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ret = PTR_ERR_OR_ZERO(crtc_state);
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if (ret)
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goto err;
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goto out;
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/* force a restore */
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crtc_state->mode_changed = true;
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@ -8376,17 +8373,15 @@ static int dm_force_atomic_commit(struct drm_connector *connector)
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ret = PTR_ERR_OR_ZERO(plane_state);
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if (ret)
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goto err;
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goto out;
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/* Call commit internally with the state we just constructed */
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ret = drm_atomic_commit(state);
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if (!ret)
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return 0;
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|
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err:
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DRM_ERROR("Restoring old state failed with %i\n", ret);
|
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out:
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drm_atomic_state_put(state);
|
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if (ret)
|
||||
DRM_ERROR("Restoring old state failed with %i\n", ret);
|
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|
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return ret;
|
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}
|
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|
|
|
|||
|
|
@ -833,6 +833,9 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
|
|||
if (computed_streams[i])
|
||||
continue;
|
||||
|
||||
if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
|
||||
return false;
|
||||
|
||||
mutex_lock(&aconnector->mst_mgr.lock);
|
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if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
|
||||
mutex_unlock(&aconnector->mst_mgr.lock);
|
||||
|
|
@ -850,7 +853,8 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
|
|||
stream = dc_state->streams[i];
|
||||
|
||||
if (stream->timing.flags.DSC == 1)
|
||||
dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream);
|
||||
if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -2679,8 +2679,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
struct dc_surface_update *srf_updates,
|
||||
int surface_count,
|
||||
struct dc_stream_state *stream,
|
||||
struct dc_stream_update *stream_update,
|
||||
struct dc_state *state)
|
||||
struct dc_stream_update *stream_update)
|
||||
{
|
||||
const struct dc_stream_status *stream_status;
|
||||
enum surface_update_type update_type;
|
||||
|
|
@ -2699,6 +2698,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
|
||||
|
||||
if (update_type >= UPDATE_TYPE_FULL) {
|
||||
struct dc_plane_state *new_planes[MAX_SURFACES];
|
||||
|
||||
memset(new_planes, 0, sizeof(new_planes));
|
||||
|
||||
for (i = 0; i < surface_count; i++)
|
||||
new_planes[i] = srf_updates[i].surface;
|
||||
|
||||
/* initialize scratch memory for building context */
|
||||
context = dc_create_state(dc);
|
||||
|
|
@ -2707,15 +2712,21 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
return;
|
||||
}
|
||||
|
||||
dc_resource_state_copy_construct(state, context);
|
||||
dc_resource_state_copy_construct(
|
||||
dc->current_state, context);
|
||||
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
|
||||
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
|
||||
new_pipe->plane_state->force_full_update = true;
|
||||
/*remove old surfaces from context */
|
||||
if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
|
||||
DC_ERROR("Failed to remove streams for new validate context!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* add surface to context */
|
||||
if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
|
||||
DC_ERROR("Failed to add streams for new validate context!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -892,14 +892,14 @@ static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_inte
|
|||
|
||||
switch (dpcd_aux_read_interval) {
|
||||
case 0x01:
|
||||
aux_rd_interval_us = 400;
|
||||
break;
|
||||
case 0x02:
|
||||
aux_rd_interval_us = 4000;
|
||||
break;
|
||||
case 0x03:
|
||||
case 0x02:
|
||||
aux_rd_interval_us = 8000;
|
||||
break;
|
||||
case 0x03:
|
||||
aux_rd_interval_us = 12000;
|
||||
break;
|
||||
case 0x04:
|
||||
aux_rd_interval_us = 16000;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -283,8 +283,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
struct dc_surface_update *srf_updates,
|
||||
int surface_count,
|
||||
struct dc_stream_state *stream,
|
||||
struct dc_stream_update *stream_update,
|
||||
struct dc_state *state);
|
||||
struct dc_stream_update *stream_update);
|
||||
/*
|
||||
* Log the current stream state.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -906,6 +906,8 @@ enum dcn20_clk_src_array_id {
|
|||
DCN20_CLK_SRC_PLL0,
|
||||
DCN20_CLK_SRC_PLL1,
|
||||
DCN20_CLK_SRC_PLL2,
|
||||
DCN20_CLK_SRC_PLL3,
|
||||
DCN20_CLK_SRC_PLL4,
|
||||
DCN20_CLK_SRC_TOTAL_DCN21
|
||||
};
|
||||
|
||||
|
|
@ -2030,6 +2032,14 @@ static bool dcn21_resource_construct(
|
|||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL2,
|
||||
&clk_src_regs[2], false);
|
||||
pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
|
||||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL3,
|
||||
&clk_src_regs[3], false);
|
||||
pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
|
||||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL4,
|
||||
&clk_src_regs[4], false);
|
||||
|
||||
pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
|
||||
|
||||
|
|
|
|||
|
|
@ -591,14 +591,17 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
|
|||
gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
|
||||
gpu_metrics->average_cpu_power = metrics.Power[0];
|
||||
gpu_metrics->average_soc_power = metrics.Power[1];
|
||||
gpu_metrics->average_gfx_power = metrics.Power[2];
|
||||
memcpy(&gpu_metrics->average_core_power[0],
|
||||
&metrics.CorePower[0],
|
||||
sizeof(uint16_t) * 8);
|
||||
|
||||
gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
|
||||
gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
|
||||
gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
|
||||
gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
|
||||
gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
|
||||
gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
|
||||
|
||||
memcpy(&gpu_metrics->current_coreclk[0],
|
||||
&metrics.CoreFrequency[0],
|
||||
|
|
|
|||
Loading…
Reference in a new issue