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drm/amd/powerplay: add some display/powerplay interfaces
New interfaces needed to handle the new clock trees and bandwidth requirements on vega10. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a2dd023a77
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d018772748
5 changed files with 191 additions and 1 deletions
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@ -1349,6 +1349,100 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
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return ret;
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}
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int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret != 0)
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return ret;
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if (!clocks)
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return -EINVAL;
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mutex_lock(&pp_handle->pp_lock);
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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}
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int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret != 0)
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return ret;
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if (!clocks)
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return -EINVAL;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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mutex_lock(&pp_handle->pp_lock);
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ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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}
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int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret != 0)
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return ret;
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if (!wm_with_clock_ranges)
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return -EINVAL;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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mutex_lock(&pp_handle->pp_lock);
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ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
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wm_with_clock_ranges);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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}
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int amd_powerplay_display_clock_voltage_request(void *handle,
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struct pp_display_clock_request *clock)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret != 0)
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return ret;
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if (!clock)
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return -EINVAL;
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hwmgr = ((struct pp_instance *)handle)->hwmgr;
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mutex_lock(&pp_handle->pp_lock);
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ret = phm_display_clock_voltage_request(hwmgr, clock);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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}
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *clocks)
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{
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@ -443,6 +443,55 @@ int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, s
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}
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int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
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}
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int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
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}
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int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
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return -EINVAL;
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return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
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wm_with_clock_ranges);
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}
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int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->display_clock_voltage_request)
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return -EINVAL;
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return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
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}
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int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
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{
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PHM_FUNC_CHECK(hwmgr);
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@ -28,6 +28,7 @@
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#include <linux/errno.h>
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#include "amd_shared.h"
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#include "cgs_common.h"
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#include "dm_pp_interface.h"
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extern const struct amd_ip_funcs pp_ip_funcs;
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extern const struct amd_powerplay_funcs pp_dpm_funcs;
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@ -226,6 +227,8 @@ struct amd_pp_display_configuration {
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* higher latency not allowed.
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*/
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uint32_t dce_tolerable_mclk_in_active_latency;
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uint32_t min_dcef_set_clk;
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uint32_t min_dcef_deep_sleep_set_clk;
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};
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struct amd_pp_simple_clock_info {
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@ -266,7 +269,11 @@ struct amd_pp_clock_info {
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enum amd_pp_clock_type {
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amd_pp_disp_clock = 1,
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amd_pp_sys_clock,
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amd_pp_mem_clock
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amd_pp_mem_clock,
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amd_pp_dcef_clock,
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amd_pp_soc_clock,
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amd_pp_pixel_clock,
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amd_pp_phy_clock
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};
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#define MAX_NUM_CLOCKS 16
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@ -303,6 +310,11 @@ struct pp_gpu_power {
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uint32_t average_gpu_power;
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};
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struct pp_display_clock_request {
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enum amd_pp_clock_type clock_type;
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uint32_t clock_freq_in_khz;
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};
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#define PP_GROUP_MASK 0xF0000000
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#define PP_GROUP_SHIFT 28
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@ -405,6 +417,20 @@ int amd_powerplay_get_clock_by_type(void *handle,
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enum amd_pp_clock_type type,
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struct amd_pp_clocks *clocks);
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int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int amd_powerplay_display_clock_voltage_request(void *handle,
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struct pp_display_clock_request *clock);
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *output);
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@ -419,6 +419,17 @@ extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const st
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extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
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extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock);
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extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
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#endif /* _HARDWARE_MANAGER_H_ */
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@ -347,6 +347,16 @@ struct pp_hwmgr_func {
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int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
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const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
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int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
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int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock);
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int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
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int (*power_off_asic)(struct pp_hwmgr *hwmgr);
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int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
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