mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-07 03:18:31 +00:00
KVM: nVMX: fix msr bitmaps to prevent L2 from accessing L0 x2APIC
msr bitmap can be used to avoid a VM exit (interception) on guest MSR
accesses. In some configurations of VMX controls, the guest can even
directly access host's x2APIC MSRs. See SDM 29.5 VIRTUALIZING MSR-BASED
APIC ACCESSES.
L2 could read all L0's x2APIC MSRs and write TPR, EOI, and SELF_IPI.
To do so, L1 would first trick KVM to disable all possible interceptions
by enabling APICv features and then would turn those features off;
nested_vmx_merge_msr_bitmap() only disabled interceptions, so VMX would
not intercept previously enabled MSRs even though they were not safe
with the new configuration.
Correctly re-enabling interceptions is not enough as a second bug would
still allow L1+L2 to access host's MSRs: msr bitmap was shared for all
VMCSs, so L1 could trigger a race to get the desired combination of msr
bitmap and VMX controls.
This fix allocates a msr bitmap for every L1 VCPU, allows only safe
x2APIC MSRs from L1's msr bitmap, and disables msr bitmaps if they would
have to intercept everything anyway.
Fixes: 3af18d9c5f
("KVM: nVMX: Prepare for using hardware MSR bitmap")
Reported-by: Jim Mattson <jmattson@google.com>
Suggested-by: Wincy Van <fanwenyi0529@gmail.com>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
This commit is contained in:
parent
184ca82348
commit
d048c09821
1 changed files with 44 additions and 63 deletions
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@ -435,6 +435,8 @@ struct nested_vmx {
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bool pi_pending;
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u16 posted_intr_nv;
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unsigned long *msr_bitmap;
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struct hrtimer preemption_timer;
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bool preemption_timer_expired;
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@ -924,7 +926,6 @@ static unsigned long *vmx_msr_bitmap_legacy;
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static unsigned long *vmx_msr_bitmap_longmode;
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static unsigned long *vmx_msr_bitmap_legacy_x2apic;
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static unsigned long *vmx_msr_bitmap_longmode_x2apic;
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static unsigned long *vmx_msr_bitmap_nested;
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static unsigned long *vmx_vmread_bitmap;
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static unsigned long *vmx_vmwrite_bitmap;
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@ -2508,7 +2509,7 @@ static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
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unsigned long *msr_bitmap;
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if (is_guest_mode(vcpu))
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msr_bitmap = vmx_msr_bitmap_nested;
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msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
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else if (cpu_has_secondary_exec_ctrls() &&
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(vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
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SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
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@ -6363,13 +6364,6 @@ static __init int hardware_setup(void)
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if (!vmx_msr_bitmap_longmode_x2apic)
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goto out4;
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if (nested) {
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vmx_msr_bitmap_nested =
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(unsigned long *)__get_free_page(GFP_KERNEL);
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if (!vmx_msr_bitmap_nested)
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goto out5;
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}
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vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
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if (!vmx_vmread_bitmap)
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goto out6;
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@ -6392,8 +6386,6 @@ static __init int hardware_setup(void)
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memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
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memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
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if (nested)
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memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
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if (setup_vmcs_config(&vmcs_config) < 0) {
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r = -EIO;
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@ -6529,9 +6521,6 @@ static __init int hardware_setup(void)
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out7:
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free_page((unsigned long)vmx_vmread_bitmap);
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out6:
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if (nested)
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free_page((unsigned long)vmx_msr_bitmap_nested);
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out5:
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free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
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out4:
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free_page((unsigned long)vmx_msr_bitmap_longmode);
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@ -6557,8 +6546,6 @@ static __exit void hardware_unsetup(void)
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free_page((unsigned long)vmx_io_bitmap_a);
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free_page((unsigned long)vmx_vmwrite_bitmap);
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free_page((unsigned long)vmx_vmread_bitmap);
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if (nested)
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free_page((unsigned long)vmx_msr_bitmap_nested);
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free_kvm_area();
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}
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@ -6995,16 +6982,21 @@ static int handle_vmon(struct kvm_vcpu *vcpu)
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return 1;
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}
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if (cpu_has_vmx_msr_bitmap()) {
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vmx->nested.msr_bitmap =
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(unsigned long *)__get_free_page(GFP_KERNEL);
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if (!vmx->nested.msr_bitmap)
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goto out_msr_bitmap;
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}
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vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
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if (!vmx->nested.cached_vmcs12)
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return -ENOMEM;
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goto out_cached_vmcs12;
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if (enable_shadow_vmcs) {
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shadow_vmcs = alloc_vmcs();
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if (!shadow_vmcs) {
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kfree(vmx->nested.cached_vmcs12);
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return -ENOMEM;
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}
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if (!shadow_vmcs)
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goto out_shadow_vmcs;
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/* mark vmcs as shadow */
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shadow_vmcs->revision_id |= (1u << 31);
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/* init shadow vmcs */
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@ -7024,6 +7016,15 @@ static int handle_vmon(struct kvm_vcpu *vcpu)
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skip_emulated_instruction(vcpu);
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nested_vmx_succeed(vcpu);
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return 1;
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out_shadow_vmcs:
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kfree(vmx->nested.cached_vmcs12);
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out_cached_vmcs12:
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free_page((unsigned long)vmx->nested.msr_bitmap);
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out_msr_bitmap:
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return -ENOMEM;
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}
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/*
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@ -7098,6 +7099,10 @@ static void free_nested(struct vcpu_vmx *vmx)
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vmx->nested.vmxon = false;
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free_vpid(vmx->nested.vpid02);
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nested_release_vmcs12(vmx);
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if (vmx->nested.msr_bitmap) {
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free_page((unsigned long)vmx->nested.msr_bitmap);
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vmx->nested.msr_bitmap = NULL;
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}
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if (enable_shadow_vmcs)
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free_vmcs(vmx->nested.current_shadow_vmcs);
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kfree(vmx->nested.cached_vmcs12);
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@ -9472,8 +9477,10 @@ static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
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{
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int msr;
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struct page *page;
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unsigned long *msr_bitmap;
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unsigned long *msr_bitmap_l1;
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unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
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/* This shortcut is ok because we support only x2APIC MSRs so far. */
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if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
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return false;
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@ -9482,63 +9489,37 @@ static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
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WARN_ON(1);
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return false;
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}
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msr_bitmap = (unsigned long *)kmap(page);
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if (!msr_bitmap) {
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msr_bitmap_l1 = (unsigned long *)kmap(page);
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if (!msr_bitmap_l1) {
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nested_release_page_clean(page);
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WARN_ON(1);
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return false;
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}
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memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
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if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
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if (nested_cpu_has_apic_reg_virt(vmcs12))
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for (msr = 0x800; msr <= 0x8ff; msr++)
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap,
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vmx_msr_bitmap_nested,
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msr_bitmap_l1, msr_bitmap_l0,
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msr, MSR_TYPE_R);
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/* TPR is allowed */
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nested_vmx_disable_intercept_for_msr(msr_bitmap,
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vmx_msr_bitmap_nested,
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap_l1, msr_bitmap_l0,
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APIC_BASE_MSR + (APIC_TASKPRI >> 4),
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MSR_TYPE_R | MSR_TYPE_W);
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if (nested_cpu_has_vid(vmcs12)) {
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/* EOI and self-IPI are allowed */
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap,
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vmx_msr_bitmap_nested,
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msr_bitmap_l1, msr_bitmap_l0,
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APIC_BASE_MSR + (APIC_EOI >> 4),
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MSR_TYPE_W);
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nested_vmx_disable_intercept_for_msr(
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msr_bitmap,
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vmx_msr_bitmap_nested,
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msr_bitmap_l1, msr_bitmap_l0,
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APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
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MSR_TYPE_W);
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}
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} else {
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/*
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* Enable reading intercept of all the x2apic
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* MSRs. We should not rely on vmcs12 to do any
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* optimizations here, it may have been modified
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* by L1.
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*/
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for (msr = 0x800; msr <= 0x8ff; msr++)
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__vmx_enable_intercept_for_msr(
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vmx_msr_bitmap_nested,
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msr,
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MSR_TYPE_R);
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__vmx_enable_intercept_for_msr(
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vmx_msr_bitmap_nested,
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APIC_BASE_MSR + (APIC_TASKPRI >> 4),
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MSR_TYPE_W);
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__vmx_enable_intercept_for_msr(
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vmx_msr_bitmap_nested,
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APIC_BASE_MSR + (APIC_EOI >> 4),
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MSR_TYPE_W);
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__vmx_enable_intercept_for_msr(
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vmx_msr_bitmap_nested,
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APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
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MSR_TYPE_W);
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}
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kunmap(page);
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nested_release_page_clean(page);
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@ -9957,10 +9938,10 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
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}
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if (cpu_has_vmx_msr_bitmap() &&
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exec_control & CPU_BASED_USE_MSR_BITMAPS) {
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nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
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/* MSR_BITMAP will be set by following vmx_set_efer. */
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} else
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exec_control & CPU_BASED_USE_MSR_BITMAPS &&
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nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
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; /* MSR_BITMAP will be set by following vmx_set_efer. */
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else
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exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
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/*
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