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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
drm/vc4: Move validation's current/max ip into the validation struct.
Reduces the argument count for some of the functions, and will be used more with the upcoming looping support. Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
parent
af713795c5
commit
d0566c2a2f
1 changed files with 30 additions and 24 deletions
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@ -40,6 +40,14 @@
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#include "vc4_qpu_defines.h"
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struct vc4_shader_validation_state {
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/* Current IP being validated. */
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uint32_t ip;
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/* IP at the end of the BO, do not read shader[max_ip] */
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uint32_t max_ip;
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uint64_t *shader;
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struct vc4_texture_sample_info tmu_setup[2];
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int tmu_write_count[2];
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@ -129,11 +137,11 @@ record_texture_sample(struct vc4_validated_shader_info *validated_shader,
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}
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static bool
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check_tmu_write(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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check_tmu_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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@ -228,11 +236,11 @@ check_tmu_write(uint64_t inst,
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}
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static bool
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check_reg_write(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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check_reg_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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@ -261,7 +269,7 @@ check_reg_write(uint64_t inst,
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case QPU_W_TMU1_T:
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case QPU_W_TMU1_R:
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case QPU_W_TMU1_B:
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return check_tmu_write(inst, validated_shader, validation_state,
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return check_tmu_write(validated_shader, validation_state,
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is_mul);
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case QPU_W_HOST_INT:
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@ -294,10 +302,10 @@ check_reg_write(uint64_t inst,
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}
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static void
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track_live_clamps(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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track_live_clamps(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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@ -369,10 +377,10 @@ track_live_clamps(uint64_t inst,
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}
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static bool
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check_instruction_writes(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state)
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{
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uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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bool ok;
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@ -382,12 +390,10 @@ check_instruction_writes(uint64_t inst,
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return false;
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}
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ok = (check_reg_write(inst, validated_shader, validation_state,
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false) &&
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check_reg_write(inst, validated_shader, validation_state,
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true));
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ok = (check_reg_write(validated_shader, validation_state, false) &&
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check_reg_write(validated_shader, validation_state, true));
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track_live_clamps(inst, validated_shader, validation_state);
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track_live_clamps(validated_shader, validation_state);
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return ok;
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}
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@ -417,30 +423,30 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
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{
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bool found_shader_end = false;
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int shader_end_ip = 0;
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uint32_t ip, max_ip;
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uint64_t *shader;
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uint32_t ip;
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struct vc4_validated_shader_info *validated_shader;
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struct vc4_shader_validation_state validation_state;
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int i;
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memset(&validation_state, 0, sizeof(validation_state));
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validation_state.shader = shader_obj->vaddr;
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validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
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for (i = 0; i < 8; i++)
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validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
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for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
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validation_state.live_min_clamp_offsets[i] = ~0;
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shader = shader_obj->vaddr;
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max_ip = shader_obj->base.size / sizeof(uint64_t);
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validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
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if (!validated_shader)
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return NULL;
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for (ip = 0; ip < max_ip; ip++) {
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uint64_t inst = shader[ip];
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for (ip = 0; ip < validation_state.max_ip; ip++) {
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uint64_t inst = validation_state.shader[ip];
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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validation_state.ip = ip;
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switch (sig) {
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case QPU_SIG_NONE:
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case QPU_SIG_WAIT_FOR_SCOREBOARD:
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@ -450,7 +456,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
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case QPU_SIG_LOAD_TMU1:
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case QPU_SIG_PROG_END:
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case QPU_SIG_SMALL_IMM:
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if (!check_instruction_writes(inst, validated_shader,
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if (!check_instruction_writes(validated_shader,
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&validation_state)) {
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DRM_ERROR("Bad write at ip %d\n", ip);
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goto fail;
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@ -467,7 +473,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
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break;
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case QPU_SIG_LOAD_IMM:
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if (!check_instruction_writes(inst, validated_shader,
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if (!check_instruction_writes(validated_shader,
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&validation_state)) {
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DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
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goto fail;
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@ -487,7 +493,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
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break;
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}
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if (ip == max_ip) {
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if (ip == validation_state.max_ip) {
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DRM_ERROR("shader failed to terminate before "
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"shader BO end at %zd\n",
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shader_obj->base.size);
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