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MIPS: Loongson-3: Fix CPU UART irq delivery problem
Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to other CPUs) may cause interrupts be lost, especially in multi-package machines (Package-0's UART irq cannot be delivered to others). So make mask_loongson_irq() and unmask_loongson_irq() be no-ops. The original problem (UART IRQ may deliver to any core) is also because of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to remove all of the stuff. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20433/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
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1 changed files with 3 additions and 40 deletions
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@ -102,45 +102,8 @@ static struct irqaction cascade_irqaction = {
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.name = "cascade",
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};
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static inline void mask_loongson_irq(struct irq_data *d)
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{
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clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_disable_hazard();
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/* Workaround: UART IRQ may deliver to any core */
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if (d->irq == LOONGSON_UART_IRQ) {
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int cpu = smp_processor_id();
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int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
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int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
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u64 intenclr_addr = smp_group[node_id] |
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(u64)(&LOONGSON_INT_ROUTER_INTENCLR);
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u64 introuter_lpc_addr = smp_group[node_id] |
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(u64)(&LOONGSON_INT_ROUTER_LPC);
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*(volatile u32 *)intenclr_addr = 1 << 10;
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*(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
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}
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}
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static inline void unmask_loongson_irq(struct irq_data *d)
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{
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/* Workaround: UART IRQ may deliver to any core */
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if (d->irq == LOONGSON_UART_IRQ) {
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int cpu = smp_processor_id();
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int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
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int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
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u64 intenset_addr = smp_group[node_id] |
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(u64)(&LOONGSON_INT_ROUTER_INTENSET);
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u64 introuter_lpc_addr = smp_group[node_id] |
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(u64)(&LOONGSON_INT_ROUTER_LPC);
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*(volatile u32 *)intenset_addr = 1 << 10;
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*(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
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}
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set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_enable_hazard();
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}
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static inline void mask_loongson_irq(struct irq_data *d) { }
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static inline void unmask_loongson_irq(struct irq_data *d) { }
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/* For MIPS IRQs which shared by all cores */
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static struct irq_chip loongson_irq_chip = {
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@ -183,7 +146,7 @@ void __init mach_init_irq(void)
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chip->irq_set_affinity = plat_set_irq_affinity;
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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&loongson_irq_chip, handle_level_irq);
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&loongson_irq_chip, handle_percpu_irq);
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/* setup HT1 irq */
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setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
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