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MIPS: Lantiq: Add pmu bits for ar10 and grx390
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11388/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 56 additions and 1 deletions
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@ -110,6 +110,7 @@ static u32 pmu_clk_cr_b[] = {
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#define PMU_PPE_TC BIT(21)
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#define PMU_PPE_EMA BIT(22)
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#define PMU_PPE_DPLUM BIT(23)
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#define PMU_PPE_DP BIT(23)
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#define PMU_PPE_DPLUS BIT(24)
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#define PMU_USB1_P BIT(26)
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#define PMU_USB1 BIT(27)
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@ -118,10 +119,27 @@ static u32 pmu_clk_cr_b[] = {
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#define PMU_GPHY BIT(30)
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#define PMU_PCIE_CLK BIT(31)
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#define PMU1_PCIE_PHY BIT(0)
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#define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
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#define PMU1_PCIE_CTL BIT(1)
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#define PMU1_PCIE_PDI BIT(4)
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#define PMU1_PCIE_MSI BIT(5)
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#define PMU1_CKE BIT(6)
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#define PMU1_PCIE1_CTL BIT(17)
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#define PMU1_PCIE1_PDI BIT(20)
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#define PMU1_PCIE1_MSI BIT(21)
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#define PMU1_PCIE2_CTL BIT(25)
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#define PMU1_PCIE2_PDI BIT(26)
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#define PMU1_PCIE2_MSI BIT(27)
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#define PMU_ANALOG_USB0_P BIT(0)
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#define PMU_ANALOG_USB1_P BIT(1)
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#define PMU_ANALOG_PCIE0_P BIT(8)
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#define PMU_ANALOG_PCIE1_P BIT(9)
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#define PMU_ANALOG_PCIE2_P BIT(10)
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#define PMU_ANALOG_DSL_AFE BIT(16)
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#define PMU_ANALOG_DCDC_2V5 BIT(17)
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#define PMU_ANALOG_DCDC_1VX BIT(18)
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#define PMU_ANALOG_DCDC_1V0 BIT(19)
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#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
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#define pmu_r32(x) ltq_r32(pmu_membase + (x))
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@ -448,6 +466,22 @@ void __init ltq_soc_init(void)
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clkdev_add_pci();
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}
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if (of_machine_is_compatible("lantiq,grx390") ||
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of_machine_is_compatible("lantiq,ar10")) {
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clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
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clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
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/* rc 0 */
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clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
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clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
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clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
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clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
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/* rc 1 */
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clkdev_add_pmu("19000000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
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clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
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clkdev_add_pmu("19000000.pcie", "pdi", 1, 1, PMU1_PCIE1_PDI);
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clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
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}
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if (of_machine_is_compatible("lantiq,ase")) {
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if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
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clkdev_add_static(CLOCK_266M, CLOCK_133M,
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@ -461,6 +495,27 @@ void __init ltq_soc_init(void)
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clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
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clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
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} else if (of_machine_is_compatible("lantiq,grx390")) {
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clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
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ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
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clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
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clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
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/* rc 2 */
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clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
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clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
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clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
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clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
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clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH | PMU_PPE_DP);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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} else if (of_machine_is_compatible("lantiq,ar10")) {
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clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
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ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
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clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
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clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
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clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH |
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PMU_PPE_DP | PMU_PPE_TC);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
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} else if (of_machine_is_compatible("lantiq,vr9")) {
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clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
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