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drm/i915/psr: Add enable_source vfunc. 

Continue on VLV PSR split with vfunc, let's also create one
for enabling source.

Also since we are touching *_enable_source functions let's
fix a comment with wrong name for vlv's one.

v2: Fix typo on commit message (DK).

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-12-rodrigo.vivi@intel.com
This commit is contained in:
Rodrigo Vivi 2017-09-07 16:00:41 -07:00
parent 49ad316f87
commit d0d5e0d7b1
2 changed files with 6 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1181,6 +1181,8 @@ struct i915_psr {
bool colorimetry_support;
bool alpm;
void (*enable_source)(struct intel_dp *,
const struct intel_crtc_state *);
void (*disable_source)(struct intel_dp *,
const struct intel_crtc_state *);
void (*enable_sink)(struct intel_dp *);

14
drivers/gpu/drm/i915/intel_psr.c
View File

@ -542,14 +542,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
dev_priv->psr.setup_vsc(intel_dp, crtc_state);
dev_priv->psr.enable_sink(intel_dp);
if (HAS_DDI(dev_priv)) {
hsw_psr_enable_source(intel_dp, crtc_state);
} else {
vlv_psr_enable_source(intel_dp, crtc_state);
}
dev_priv->psr.enable_source(intel_dp, crtc_state);
dev_priv->psr.enabled = intel_dp;
if (INTEL_GEN(dev_priv) >= 9) {
@ -777,8 +770,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
* directly once PSR State 4 that is active with single frame
* update can be skipped. PSR_state 5 that is PSR exit then
* Hardware is responsible to transition back to PSR_state 1
* that is PSR inactive. Same state after
* vlv_edp_psr_enable_source.
* that is PSR inactive. Same state after vlv_psr_enable_source.
*/
val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
I915_WRITE(VLV_PSRCTL(pipe), val);
@ -973,11 +965,13 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->psr.lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->psr.enable_source = vlv_psr_enable_source;
dev_priv->psr.disable_source = vlv_psr_disable;
dev_priv->psr.enable_sink = vlv_psr_enable_sink;
dev_priv->psr.activate = vlv_psr_activate;
dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
} else {
dev_priv->psr.enable_source = hsw_psr_enable_source;
dev_priv->psr.disable_source = hsw_psr_disable;
dev_priv->psr.enable_sink = hsw_psr_enable_sink;
dev_priv->psr.activate = hsw_psr_activate;